ISL6333 Datasheet, PDF (26/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
Compensating Dynamic VID Transitions
During a VID transition, the resulting change in voltage on the
FB pin and the COMP pin causes an AC current to flow through
the error amplifier compensation components from the FB to
the COMP pin. This current then flows through the feedback
resistor, R_FB, and can cause the output voltage to overshoot or
undershoot at the end of the VID transition. In order to ensure
the smooth transition of the output voltage during a VID
change, a VID-on-the-fly compensation network is required.
This network is composed of a resistor and capacitor in series,
R_DVC and C_DVC, between the DVC and the FB pin.
This VID-on-the-fly compensation network works by
sourcing AC current into the FB node to offset the effects of
the AC current flowing from the FB to the COMP pin during a
VID transition. To create this compensation current the
controllers set the voltage on the DVC pin to be 2x the
voltage on the REF pin. Since the error amplifier forces the
voltage on the FB pin and the REF pin to be equal, the
resulting voltage across the series RC between DVC and FB
is equal to the REF pin voltage. The RC compensation
components, R_DVC and C_DVC, can then be selected to
create the desired amount of compensation current.
VDIFF
R_FB ^IDVC ^{= I}C
I_C
I_DVC
DVC
C_DVC
R_DVC
C_C
FB
R_C
COMP
REF
C_REF
x2
V_DAC
-
+ _ERROR
AMPLIFIER
ISL6333 INTERNAL CIRCUIT
FIGURE 10. DYNAMIC VID COMPENSATION NETWORK
The amount of compensation current required is dependant on
the modulator gain of the system, K1, and the error amplifier R-
C components, R_C and C_C, that are in series between the FB
and COMP pins. Use Equations 15, 16, and 17 to calculate the
RC component values, R_DVC and C_DVC, for the VID-on-the-fly
compensation network. For these equations: V_IN is the input
voltage for the power train; V_P-P is the oscillator ramp
amplitude (1.5V); and R_C and C_C are the error amplifier R-C
components between the FB and COMP pins.
K1
=
-^V-----^I-^N----
V_PP
A
=
-----^K-----¹------
K1 – 1
(EQ. 15)
R_DVC = A × R_C
(EQ. 16)
C_DVC
=
C_-----C--
A
(EQ. 17)
Driver Operation
Adaptive Zero Shoot-Through Deadtime Control
The integrated drivers incorporate an adaptive deadtime control
technique to minimize deadtime and to prevent the upper and
lower MOSFETs from conducting simultaneously. This results
in high efficiency from the reduced freewheeling time of the
lower MOSFET body-diode conduction. This is accomplished
by ensuring either rising gate turns on its MOSFET with
minimum and sufficient delay after the other has turned off.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches 1.75V. At this time the UGATE is
released to rise. Once the PHASE is high, the advanced
adaptive shoot-through circuitry monitors the PHASE and
UGATE voltages during a PWM falling edge and the
subsequent UGATE turn-off. If either the UGATE falls to less
than 1.75V above the PHASE or the PHASE falls to less than
+0.8V, the LGATE is released to turn on.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor should have a maximum voltage
rating that’s at least 30% above PVCC and its capacitance
value can be chosen from Equation 18:
C_B
O
O
T
_CAP
≥
----------^Q-----^G----^A----^T---^E-----------
Δ V_{B O O T _CAP}
Q_GATE=
Q_{-----G-----1----}⋅_---P_-----V_----C_-----C_---
V_GS1
⋅
N_Q1
(EQ. 18)
where Q_G1 is the amount of gate charge per upper MOSFET
at V_GS1 gate-source voltage and N_Q1 is the number of
control MOSFETs. The ΔV_{BOOT_CAP} term is defined as the
allowable droop in the rail of the upper gate drive.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2 _20nC
Q_GATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV_{BOOT_CAP} (V)
FIGURE 11. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
26
FN6520.3
October 8, 2010