ISL6333 Datasheet, PDF(31/40 Page) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

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ISL6333 Datasheet, PDF (31/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

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ISL6333, ISL6333A, ISL6333B, ISL6333C

OUTPUT CURRENT, 50A/DIV

OUTPUT VOLTAGE,

500mV/DIV

FIGURE 19. OVERCURRENT BEHAVIOR IN HICCUP MODE

Individual Channel Overcurrent Limiting

The controllers have the ability to limit the current in each

individual channel without shutting down the entire regulator.

This is accomplished by continuously comparing the sensed

currents of each channel with a constant 140ÂµA OCL

reference current, as shown in Figure 18. If a channelâs

individual sensed current exceeds this OCL limit, the UGATE

signal of that channel is immediately forced low, and the

LGATE signal is forced high. This turns off the upper

MOSFET(s), turns on the lower MOSFET(s), and stops the

rise of current in that channel, forcing the current in the

channel to decrease. That channelâs UGATE signal will not

be able to return high until the sensed channel current falls

back below the 140ÂµA reference.

During VID-on-the-fly transitions the OCL trip level is

boosted to prevent false overcurrent limiting events that can

occur. Starting from the beginning of a dynamic VID

transition, the overcurrent trip level is boosted to 196ÂµA. The

OCL level will stay at this boosted level until 50Âµs after the

end of the dynamic VID transition, at which point it will return

to the typical 140ÂµA trip level.

MOSFETs General Design Guide

This design guide is intended to provide a high-level

explanation of the steps necessary to create a multi-phase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced in the

following. In addition to this guide, Intersil provides complete

reference designs that include schematics, bills of materials,

and example board layouts for all common microprocessor

applications.

Power Stages

The first step in designing a multi-phase converter is to

determine the number of phases. This determination

depends heavily on the cost analysis, which in turn depends

on system constraints that differ from one design to the next.

Principally, the designer will be concerned with whether

components can be mounted on both sides of the circuit

board, whether through-hole components are permitted, the

total board space available for power-supply circuitry, and

the maximum amount of load current. Generally speaking,

the most economical solutions are those in which each

phase handles between 25A and 30A. All surface-mount

designs will tend toward the lower end of this current range.

If through-hole MOSFETs and inductors can be used, higher

per-phase currents are possible. In cases where board

space is the limiting constraint, current can be pushed as

high as 40A per phase, but these designs require heat sinks

and forced air to cool the MOSFETs, inductors and

heat-dissipating surfaces.

MOSFETS

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct, the switching frequency,

the capability of the MOSFETs to dissipate heat, and the

availability and nature of heat sinking and air flow.

LOWER MOSFET POWER CALCULATION

The calculation for power loss in the lower MOSFET is

simple, since virtually all of the loss in the lower MOSFET is

due to current conducted through the channel resistance

(rDS(ON)). In Equation 24, IM is the maximum continuous

output current, IP-P is the peak-to-peak inductor current (see

Equation 1), and d is the duty cycle (VOUT/VIN).

PLOW(1)

rDS(ON) â

I--M---ââ

â Nâ

I--L----(--P------P----)--2-â---(---1----â-----d----)

(EQ. 24)

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the dead

time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the

diode forward voltage at IM, VD(ON), the switching frequency,

fS, and the length of dead times, td1 and td2, at the beginning

and the end of the lower-MOSFET conduction interval

respectively.

PLOW(2)

VD(ON) â fS

I--M----

I--P---2----P---â ââ

td1

I--M----

I--P---2----P---â âââ

td2

(EQ. 25)

The total maximum power dissipated in each lower MOSFET

is approximated by the summation of PLOW(1) and PLOW(2).

UPPER MOSFET POWER CALCULATION

In addition to rDS(ON) losses, a large portion of the

upper-MOSFET losses are due to currents conducted across

the input voltage (VIN) during switching. Since a substantially

higher portion of the upper-MOSFET losses are dependent on

switching frequency, the power calculation is more complex.

Upper MOSFET losses can be divided into separate

components involving the upper-MOSFET switching times,

the lower-MOSFET body-diode reverse-recovery charge, Qrr,

and the upper MOSFET rDS(ON) conduction loss.

FN6520.3

October 8, 2010

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