ISL6277A Datasheet, PDF (36/38 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0

ISL6277A PIN
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ISL6277A
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6277A CONTROLLER (Continued)
SYMBOL
LAYOUT GUIDELINES
FB2
Place the compensation components in general proximity of the controller.
FB
COMP
PGOOD
No special consideration.
BOOT1
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
UGATE1
PHASE1
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE1 to the Core VR
Channel 1 high-side MOSFET source pin instead of a general connection to PHASE1 copper is recommended for
better performance.
LGATE1
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
PWM_Y
No special considerations.
VDD
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor
in close proximity to the pin with the filter resistor nearby the IC.
VDDP
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor
in close proximity to the pin.
LGATE2
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
PHASE2
UGATE2
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE2 to the Core VR
Channel 2 high-side MOSFET source pin instead of a general connection to PHASE2 copper is recommended for
better performance.
BOOT2
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
VIN
Place the decoupling capacitor in close proximity to the pin with a short connection to the internal GND plane.
BOOTX
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
UGATEX
PHASEX
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASEX to the high-side
MOSFET source pin instead of a general connection to the PHASEX copper is recommended for better
performance.
LGATEX
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
PWM2_NB
No special considerations.
FCCM_NB
PGOOD_NB
No special consideration.
COMP_NB
Place the compensation components in general proximity of the controller.
FB_NB
VSEN_NB
Place the filter on this pin in close proximity to the controller for good coupling.
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FN8322.0
December 19, 2012