ISL6277A Datasheet, PDF (24/38 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0

ISL6277A
decay and slowly steps the DAC down with the natural decay of
the output. This allows the controller to quickly recover and move
to a high VID code if commanded. The controller issues a VOTFC
request on the SVI lines once the SVI command is decoded and
prior to reaching the final output voltage.
VOTFC requests do not take priority over telemetry per the AMD
SVI 2 specification.
SVI Data Communication Protocol
The SVI WIRE protocol is based on the I²C bus concept. Two wires
[serial clock (SVC) and serial data (SVD)], carry information
between the AMD processor (master) and VR controller (slave) on
the bus. The master initiates and terminates SVI transactions
and drives the clock, SVC, during a transaction. The AMD
processor is always the master, and the voltage regulators are
the slaves. The slave receives the SVI transactions and acts
accordingly. Mobile SVI WIRE protocol timing is based on
high-speed mode I²C. See AMD publication #48022 for
additional details.
.
TABLE 7. SERIAL VID CODES
SVID[7:0]
VOLTAGE (V)
SVID[7:0]
VOLTAGE (V)
SVID[7:0]
VOLTAGE (V)
SVID[7:0]
VOLTAGE (V)
0000_0000
1.55000
0010_0000
1.35000
0100_0000
1.15000
0110_0000
0.95000
0000_0001
1.54375
0010_0001
1.34375
0100_0001
1.14375
0110_0001
0.94375
0000_0010
1.53750
0010_0010
1.33750
0100_0010
1.13750
0110_0010
0.93750
0000_0011
1.53125
0010_0011
1.33125
0100_0011
1.13125
0110_0011
0.93125
0000_0100
1.52500
0010_0100
1.32500
0100_0100
1.12500
0110_0100
0.92500
0000_0101
1.51875
0010_0101
1.31875
0100_0101
1.11875
0110_0101
0.91875
0000_0110
1.51250
0010_0110
1.31250
0100_0110
1.11250
0110_0110
0.91250
0000_0111
1.50625
0010_0111
1.30625
0100_0111
1.10625
0110_0111
0.90625
0000_1000
1.50000
0010_1000
1.30000
0100_1000
1.10000
0110_1000
0.90000
0000_1001
1.49375
0010_1001
1.29375
0100_1001
1.09375
0110_1001
0.89375
0000_1010
1.48750
0010_1010
1.28750
0100_1010
1.08750
0110_1010
0.88750
0000_1011
1.48125
0010_1011
1.28125
0100_1011
1.08125
0110_1011
0.88125
0000_1100
1.47500
0010_1100
1.27500
0100_1100
1.07500
0110_1100
0.87500
0000_1101
1.46875
0010_1101
1.26875
0100_1101
1.06875
0110_1101
0.86875
0000_1110
1.46250
0010_1110
1.26250
0100_1110
1.06250
0110_1110
0.86250
0000_1111
1.45625
0010_1111
1.25625
0100_1111
1.05625
0110_1111
0.85625
0001_0000
1.45000
0011_0000
1.25000
0101_0000
1.05000
0111_0000
0.85000
0001_0001
1.44375
0011_0001
1.24375
0101_0001
1.04375
0111_0001
0.84375
0001_0010
1.43750
0011_0010
1.23750
0101_0010
1.03750
0111_0010
0.83750
0001_0011
1.43125
0011_0011
1.23125
0101_0011
1.03125
0111_0011
0.83125
0001_0100
1.42500
0011_0100
1.22500
0101_0100
1.02500
0111_0100
0.82500
0001_0101
1.41875
0011_0101
1.21875
0101_0101
1.01875
0111_0101
0.81875
0001_0110
1.41250
0011_0110
1.21250
0101_0110
1.01250
0111_0110
0.81250
0001_0111
1.40625
0011_0111
1.20625
0101_0111
1.00625
0111_0111
0.80625
0001_1000
1.40000
0011_1000
1.20000
0101_1000
1.00000
0111_1000
0.80000
0001_1001
1.39375
0011_1001
1.19375
0101_1001
0.99375
0111_1001
0.79375
0001_1010
1.38750
0011_1010
1.18750
0101_1010
0.98750
0111_1010
0.78750
0001_1011
1.38125
0011_1011
1.18125
0101_1011
0.98125
0111_1011
0.78125
0001_1100
1.37500
0011_1100
1.17500
0101_1100
0.97500
0111_1100
0.77500
0001_1101
1.36875
0011_1101
1.16875
0101_1101
0.96875
0111_1101
0.76875
0001_1110
1.36250
0011_1110
1.16250
0101_1110
0.96250
0111_1110
0.76250
24
FN8322.0
December 19, 2012