ISL6277A Datasheet, PDF (29/38 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0

ISL6277A
Fault Recovery
All of the previously described fault conditions can be reset by
bringing ENABLE low or by bringing VDD below the POR
threshold. When ENABLE and VDD return to their high operating
levels, the controller resets the faults and soft-start occurs.
Interface Pin Protection
The SVC and SVD pins feature protection diodes which must be
considered when removing power to VDD and VDDIO, but leaving
it applied to these pins. Figure 21 shows the basic protection on
the pins. If SVC and/or SVD are powered but VDD is not, leakage
current will flow from these pins to VDD.
SVC, SVD
INTERNAL TO
ISL6277A
VDD
and R_o connected to the pads to accurately sense the inductor
current by sensing the DCR voltage drop. The R_sum and R_o
resistors are connected in a summing network as shown, and feed
the total current information to the NTC network (consisting of
R_ntcs, R_ntc and R_p) and capacitor C_n. R_ntc is a negative
temperature coefficient (NTC) thermistor, used to temperature
compensate the inductor DCR change.
The inductor output side pads are electrically shorted in the
schematic but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
current-sensing summing network. It is recommended to use
1Ω~10Ω R_o to create quality signals. Since R_o value is much smaller
than the rest of the current sensing circuit, the following analysis
ignores it.
The summed inductor current information is presented to the
capacitor C_n. Equations 18 thru 22 describe the frequency
domain relationship between inductor total current I_o(s) and C_n
voltage V_Cn(s):
⎛
⎞
V_Cn(s)
=
⎜
⎜
⎜
⎝
-----------^R-----ⁿ---^t--^c---ⁿ----^e---^t-----------
R_ntcnet
+
-^R----^s---^u---^m---
N
×
D_-----NC-----R_{---⎟⎟⎟}
⎠
× I_o(s) × A_cs(s)
(EQ. 18)
GND
FIGURE 21. PROTECTION DEVICES ON THE SVC AND SVD PINS
Key Component Selection
Inductor DCR Current-Sensing Network
PHASE1 PHASE2 PHASE3
RSUM
RSUM
RSUM
ISUM+
L
L
L
DCR DCR
DCR
RNTCS
RP
RNTC
RO
RO
RO
+
CNVCN
-
RI
ISUM-
IO
FIGURE 22. DCR CURRENT-SENSING NETWORK
Figure 22 shows the inductor DCR current-sensing network for a
3-phase solution. An inductor current flows through the DCR and
creates a voltage drop. Each inductor has two resistors in R_sum
R_ntcnet
=
-⁽--^R----ⁿ----^t--^c---^s----+-----^R----ⁿ----^t-^c----⁾---^×-----^R----^p--
R_ntcs + R_ntc + R_p
A_cs(s)
=
----¹----+------^ω-----^s----L-----
1 + _ω-----_s-^s--_n---_s-
(EQ. 19)
(EQ. 20)
ω_L
=
D_-----C_-----R_---
L
(EQ. 21)
ω_sns
=
---------------------------¹-----------------------------
-^R----ⁿ---^t--^c---ⁿ----^e---^t---^×------^R--------^s--^N----^u-------^m------
R_n
t
cn
e
t
+
-^R----^s---^u---^m---
N
×
C_n
where N is the number of phases.
(EQ. 22)
Transfer function A_cs(s) always has unity gain at DC. The inductor
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC R_ntc
value decrease as its temperature decreases. Proper selection of
R_sum, R_ntcs, R_p and R_ntc parameters ensures that V_Cn
represents the inductor total DC current over the temperature
range of interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC
network and the R_sum resistors form a voltage divider, V_cn is
always a fraction of the inductor DCR voltage. It is recommended
to have a higher ratio of V_cn to the inductor DCR voltage so the
droop circuit has a higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: R_sum = 3.65kΩ, R_p = 11kΩ, R_ntcs = 2.61kΩ
and R_ntc = 10kΩ (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
29
FN8322.0
December 19, 2012