ISL6277A Datasheet, PDF (27/38 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0

ISL6277A
Dynamic Offset Trim
The ISL6277A supports the SVI2 ability for the processor to
manipulate the output voltage offset of the Core and Northbridge
VRs. This offset is in addition to any output voltage offset set via
the COMP resistor reader. The dynamic offset trim can disable
the COMP resistor programmed offset of either output when
‘Disable All Offset’ is selected.
TABLE 11. OFFSET TRIM DEFINITION
OFFSET TRIM [1:0]
00
01
10
11
DESCRIPTION
Disable All Offset
-25mV Change
0mV Change
+25mV Change
Telemetry
The ISL6277A can provide voltage and current information to the
AMD CPU through the telemetry system outlined by the AMD
SVI2 specification. The telemetry data is transmitted through the
SVC and SVT lines of the SVI2 interface.
Current telemetry is based on a voltage generated across a
133kΩ resistor placed from the IMON pin to GND. The current
flowing out of the IMON pin is proportional to the load current in
the VR. The I_sum current defined in “Voltage Regulation and Load
Line Implementation” on page 17, provides the base conversion
from the load current to the internal amplifier created I_sum
current. The I_sum current is then divided down by a factor of 4 to
create the IMON current which flows out of the IMON pin. The
I_sum current will measure 35µA when the load current is at full
load based on a droop current designed for 45µA at the same
load current. The difference between the I_sum current and the
droop current is provided in Equation 2. The IMON current will
measure 11.25µA at full load current for the VR and the IMON
voltage will be 1.2V. The load percentage which is reported by the
IC is based on the this voltage. When the load is 25% of the full
load, the voltage on the IMON pin will be 25% of 1.2V or 0.3V.
The SVI interface allows the selection of no telemetry, voltage
only, or voltage and current telemetry on either or both of the VR
outputs. The TFN bit along with the Core and Northbridge domain
selector bits are used by the processor to change the
functionality of telemetry; see Table 12 for more information.
TABLE 12. TFN TRUTH TABLE
TFN, CORE, NB
BITS [21,6,7]
DESCRIPTION
1,0,1
Telemetry is in voltage and current mode. Therefore,
voltage and current are sent for VDD and VDDNB
domains by the controller.
1,0,0
Telemetry is in voltage mode only. Only the voltage of
VDD and VDDNB domains is sent by the controller.
1,1,0
Telemetry is disabled.
1,1,1
Reserved
Protection Features
Core VR and Northbridge VR both provide overcurrent,
current-balance, undervoltage, and overvoltage fault protections.
The controller also provides over-temperature protection. The
following discussion is based on Core VR and also applies to the
Northbridge VR.
Overcurrent
The IMON voltage provides a means of determining the load
current at any moment in time. The overcurrent protection (OCP)
circuitry monitors the IMON voltage to determine when a fault
occurs. Based on the previous description in “Voltage Regulation
and Load Line Implementation” on page 17, the current which
flows out of the IMON pin is proportional to the I_sum current. The
I_sum current is created from the sensed voltage across Cn which is
a measure of the load current based upon the sensing element
selected. The IMON current is generated internally and is 1/4 of
the I_sum current. The EDC or IDDspike current value for the AMD
CPU load is used to set the maximum current level for droop and
the IMON voltage of 1.2V which indicates 100% loading for
telemetry. The I_sum current level at maximum load, or IDDspike, is
36µA and this translates to an IMON current level of 9µA. The
IMON resistor is 133kΩ and the 9µA flowing through the IMON
resistor results in a 1.2V level at maximum loading of the VR.
The overcurrent threshold is 1.5V on the IMON pin. Based on a
1.2V IMON voltage equating to 100% loading, the additional 0.3V
provided above this level equates to a 25% increase in load current
before an OCP fault is detected. The EDC or IDDspike current is
used to set the 1.2V on IMON for full load current. So the OCP level
is 1.25 times the EDC or IDDspike current level. This additional
margin above the EDC or IDDspike current allows the AMD CPU to
enter and exit the IDDspike performance mode without issue
unless the load current is out of line with the IDDspike expectation,
thus the need for overcurrent protection.
When the voltage on the IMON pin meets the overcurrent
threshold of 1.5V, this triggers an OCP event. Within 2µs of
detecting an OCP event, the controller asserts VR_HOT_L low to
communicate to the AMD CPU to throttle back. A fault timer
begins counting while IMON is at or above the 1.5V threshold. The
fault timer lasts 7.5µs to 11µs and then flags an OCP fault. The
controller then tri-states the active channels and goes into
shutdown. PGOOD is taken low and a fault flag from this VR is sent
to the other VR and it is shutdown within 10µs. If the IMON voltage
drops below the 1.5V threshold prior to the fault timer count
finishing, the fault timer is cleared and VR_HOT_L is taken high.
The ISL6277A also features a way-overcurrent [WOC] feature
which immediately takes the controller into shutdown. This
protection is also referred to as fast overcurrent protection for
short-circuit protection. If the IMON current reaches 15µA, WOC is
triggered. Active channels are tri-stated and the controller is
placed in shutdown and PGOOD is pulled low. There is no fault
timer on the WOC fault, the controller takes immediate action. The
other controller output is also shutdown within 10µs.
27
FN8322.0
December 19, 2012