ISL6277A Datasheet, PDF (23/38 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0

ISL6277A
TABLE 5. SWITCHING FREQUENCY SELECTION
FREQUENCY
[kHz]
COMP_NB
RANGE [kΩ]
FCCM_NB
RANGE [kΩ]
300
57.6 to OPEN
19.1 to 41.2
or
154 to OPEN
350
5.62 to 41.2
19.1 to 41.2
or
154 to OPEN
400
57.6 to OPEN
5.62 to 16.9
or
57.6 to 121
450
5.62 to 41.2
5.62 to 16.9
or
57.6 to 121
The controller monitors SVI commands to determine when to
enter power-saving mode, implement dynamic VID changes, and
shut down individual outputs.
AMD Serial VID Interface 2.0
The on-board Serial VID Interface 2.0 (SVI 2) circuitry allows the
AMD processor to directly control the Core and Northbridge
voltage reference levels within the ISL6277A. Once the PWROK
signal goes high, the IC begins monitoring the SVC and SVD pins
for instructions. The ISL6277A uses a digital-to-analog converter
(DAC) to generate a reference voltage based on the decoded SVI
value. See Figure 12 for a simple SVI interface timing diagram.
Pre-PWROK Metal VID
Typical motherboard start-up begins with the controller decoding
the SVC and SVD inputs to determine the pre-PWROK Metal VID
setting (see Table 6). Once the ENABLE input exceeds the rising
threshold, the ISL6277A decodes and locks the decoded value
into an on-board hold register.
TABLE 6. PRE-PWROK METAL VID CODES
SVC
SVD
OUTPUT VOLTAGE (V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
Once the programming pins are read, the internal DAC circuitry
begins to ramp Core and Northbridge VRs to the decoded
pre-PWROK Metal VID output level. The digital soft-start circuitry
ramps the internal reference to the target gradually at a fixed
rate of approximately 5mV/µs until the output voltage reaches
~250mV and then at the programmed slew rate. The controlled
ramp of all output voltage planes reduces in-rush current during
the soft-start interval. At the end of the soft-start interval, the
PGOOD and PGOOD_NB outputs transition high, indicating both
output planes are within regulation limits.
If the ENABLE input falls below the enable falling threshold, the
ISL6277A tri-states both outputs. PGOOD and PGOOD_NB are
pulled low with the loss of ENABLE. The Core and Northbridge VR
output voltages decay, based on output capacitance and load
leakage resistance. If bias to VDD falls below the POR level, the
ISL6277A responds in the manner previously described. Once
VDD and ENABLE rise above their respective rising thresholds,
the internal DAC circuitry re-acquires a pre-PWROK metal VID
code, and the controller soft-starts.
SVI Interface Active
Once the Core and Northbridge VRs have successfully soft-started
and PGOOD and PGOOD_NB signals transition high, PWROK can
be asserted externally to the ISL6277A. Once PWROK is asserted
to the IC, SVI instructions can begin as the controller actively
monitors the SVI interface. Details of the SVI Bus protocol are
provided in the “AMD Serial VID Interface 2.0 (SVI2)
Specification”. See AMD publication #48022.
Once a VID change command is received, the ISL6277A decodes
the information to determine which VR is affected and the VID
target is determined by the byte combinations in Table 7. The
internal DAC circuitry steps the output voltage of the VR
commanded to the new VID level. During this time, one or more
of the VR outputs could be targeted. In the event either VR is
commanded to power-off by serial VID commands, the PGOOD
signal remains asserted.
If the PWROK input is de-asserted, then the controller steps both
the Core and the Northbridge VRs back to the stored pre-PWROK
metal VID level in the holding register from initial soft-start. No
attempt is made to read the SVC and SVD inputs during this time.
If PWROK is re-asserted, then the ISL6277A SVI interface waits
for instructions.
If ENABLE goes low during normal operation, all external
MOSFETs are tri-stated and both PGOOD and PGOOD_NB are
pulled low. This event clears the pre-PWROK metal VID code and
forces the controller to check SVC and SVD upon restart, storing
the pre-PWROK metal VID code found on restart.
A POR event on either VCC or VIN during normal operation shuts
down both regulators, and both PGOOD outputs are pulled low.
The pre-PWROK metal VID code is not retained. Loss of VIN
during operation will typically cause the controller to enter a fault
condition on one or both outputs. The controller will shutdown
both Core and Northbridge VRs and latch off. The pre-PWROK
metal VID code is not retained during the process of cycling
ENABLE to reset the fault latch and restart the controller.
VID-on-the-Fly Transition
Once PWROK is high, the ISL6277A detects this flag and begins
monitoring the SVC and SVD pins for SVI instructions. The
microprocessor follows the protocol outlined in the following
sections to send instructions for VID-on-the-fly transitions. The
ISL6277A decodes the instruction and acknowledges the new
VID code. For VID codes higher than the current VID level, the
ISL6277A begins stepping the commanded VR outputs to the
new VID target at the fixed slew rate of 10mV/µs. Once the DAC
ramps to the new VID code, a VID-on-the-Fly Complete (VOTFC)
request is sent on the SVI lines.
When the VID codes are lower than the current VID level, the
ISL6277A checks the state of power state bits in the SVI
command. If power state bits are not active, the controller begins
stepping the regulator output to the new VID target. If the power
state bits are active, the controller allows the output voltage to
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FN8322.0
December 19, 2012