ISL6277A Datasheet, PDF (26/38 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0

SVC
SVD
ISL6277A
VID BITS [7:1]
VID
BIT [0]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
ACK
ACK
ACK
FIGURE 19. SVD PACKET STRUCTURE
SVI Bus Protocol
The AMD processor bus protocol is compliant with SMBus send
byte protocol for VID transactions. The AMD SVD packet structure
is shown in Figure 19. The description of each bit of the three
bytes that make up the SVI command are shown in Table 8.
During a transaction, the processor sends the start sequence
followed by each of the three bytes which end with an optional
acknowledge bit. The ISL6277A does not drive the SVD line
during the ACK bit. Finally, the processor sends the stop
sequence. After the ISL6277A has detected the stop, it can then
proceed with the commanded action from the transaction.
TABLE 8. SVD DATA PACKET
BITS
DESCRIPTION
1:5 Always 11000b
6 Core domain selector bit, if set then the following data byte
contains VID, power state, telemetry control, load line trim and
offset trim apply to the Core VR.
7 Northbridge domain selector bit, if set then the following data
byte contains VID, power state, telemetry control, load line trim
and offset trim apply to the Northbridge VR.
8 Always 0b
9 Acknowledge Bit
10 PSI0_L
11:17 VID Code bits [7:1]
18 Acknowledge Bit
19 VID Code bit [0]
20 PSI1_L
21 TFN (Telemetry Functionality)
22:24 Load Line Slope Trim
25:26 Offset Trim [1:0]
27 Acknowledge Bit
Power States
SVI2 defines two power state indicator levels, see Table 9. As
processor current consumption reduces the power state indicator
level changes to improve VR efficiency under low power
conditions.
For the Core VR operating in 3-phase mode, when PSI0_L is
asserted Channels 2 and 3 are tri-stated and Channel 1 enters
diode emulation mode to boost efficiency. When PSI1_L is
asserted, the Core VR continues to operate in this mode.
For the Northbridge VR operating in 2-phase mode, when PSI0_L
is asserted, Channel 2 is tri-stated and Channel 1 enters diode
emulation mode to boost efficiency. When PSI1_L is asserted,
the Core VR continues to operate in this fashion.
It is possible for the processor to assert or deassert PSI0_L and
PSI1_L out of order. PSI0_L takes priority over PSI1_L. If PSI0_L
is deasserted while PSI1_L is still asserted, the ISL6277A will
return the selected VR back full channel CCM operation.
TABLE 9. PSI0_L, PSI1_L AND TFN DEFINITION
FUNCTION BIT
DESCRIPTION
PSI0_L
10 Power State Indicate level 0. When this signal is
asserted (active Low) the processor is in a low
enough power state for the ISL6277A to take action
to boost efficiency by dropping phases and entering
1-Phase DE.
PSI1_L
20 Power State Indicate level 1. When this signal is
asserted (active Low) the processor is in a low
enough power state for the ISL6277A to take action
to boost efficiency by dropping phases and entering
1-Phase DE.
Dynamic Load Line Slope Trim
The ISL6277A supports the SVI2 ability for the processor to
manipulate the load line slope of the Core and Northbridge VRs
independently using the serial VID interface. The slope
manipulation applies to the initial load line slope. A load line
slope trim will typically coincide with a VOTF change. See
Table 10 for more information about the load line slope trim
feature of the ISL6277A.
TABLE 10. LOAD LINE SLOPE TRIM DEFINITION
LOAD LINE SLOPE TRIM [2:0]
DESCRIPTION
000
Disable LL
001
-40% mΩ Change
010
-20% mΩ Change
011
No Change
100
+20% mΩ Change
101
+40% mΩ Change
110
+60% mΩ Change
111
+80% mΩ Change
26
FN8322.0
December 19, 2012