ISL6277A Datasheet, PDF (34/38 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0

ISL6277A
The NTC thermistor is placed in a hot spot on the board, typically
near the upper MOSFET of Channel 1 of the respective output.
The standard resistor is placed next to the controller.
Bootstrap Capacitor Selection
The integrated gate drivers feature an internal bootstrap schottky
diode. Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
capacitor must have a maximum voltage rating above VDDP + 4V
and its capacitance value can be chosen from Equation 43:
C_BO
O
T
_CAP
≥
----------^Q-----^G----^A----^T----^E----------
Δ V_{B O O T _CAP}
(EQ. 43)
Q_GATE=
Q_{-----G-----1----}•_-----P_----V_----C_-----C_---
V_GS1
•
N_Q
1
where Q_G1 is the amount of gate charge per upper MOSFET at
V_GS1 gate-source voltage and N_Q1 is the number of control
MOSFETs. The ΔV_{BOOT_CAP} term is defined as the allowable
droop in the rail of the upper gate drive.
Optional FCCM_NB Filtering
The option for the placement of a capacitor in parallel with the
resistor from the FCCM_NB pin to GND is recommend. In the
event of a poor layout and excessive noise found on the
FCCM_NB pin, this capacitor can be populated to reduce the
noise on the pin and prevent it from corrupting the resistor read
portion of the soft-start sequence.
Layout Guidelines
PCB Layout Considerations
POWER AND SIGNAL LAYERS PLACEMENT ON THE PCB
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board. The ground-plane
layer should be adjacent to the signal layer to provide shielding.
COMPONENT PLACEMENT
There are two sets of critical components in a DC/DC converter;
the power components and the small signal components. The
power components are the most critical because they switch
large amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors, and the inductor. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each
power train. Symmetrical layout allows heat to be dissipated
equally across all power trains. Keeping the distance between
the power train and the control IC short helps keep the gate drive
traces short. These drive signals include the LGATE, UGATE,
PGND, PHASE and BOOT.
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
GND
VOUT
PHASE
NODE
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
VIN
CAPACITORS
FIGURE 33. TYPICAL POWER COMPONENT PLACEMENT
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible (see Figure 33). Input high-frequency
capacitors should be placed close to the drain of the upper
MOSFETs and the source of the lower MOSFETs. Place the output
inductor and output capacitors between the MOSFETs and the
load. High-frequency output decoupling capacitors (ceramic)
should be placed as close as possible to the decoupling target
(microprocessor), making use of the shortest connection paths to
any internal planes. Place the components in such a way that the
area under the IC has less noise traces with high dV/dt and di/dt,
such as gate signals and phase node signals.
Table 14 shows layout considerations for the ISL6277A controller
by pin.
ISL6277A PIN
BOTTOM PAD
1
2
3
4
SYMBOL
GND
ISEN2_NB
NTC_NB
IMON_NB
SVC
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6277A CONTROLLER
LAYOUT GUIDELINES
Connect this ground pad to the ground plane through a low impedance path. A minimum of 5 vias are
recommended to connect this pad to the internal ground plane layers of the PCB
Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN_NB, then through another capacitor (Cvsumn_nb)
to GND. Place Cisen capacitors as close as possible to the controller and keep the following loops small:
1. ISEN1_NB pin to ISEN2_NB pin
2. Any ISENx_NB pin to GND
The NTC thermistor must be placed close to the thermal source that is monitored to determine Northbridge
thermal throttling. Placement at the hottest spot of the Northbridge VR is recommended. Additional standard
resistors in the resistor network on this pin should be placed near the IC.
Place the IMON_NB resistor close to this pin and keep a tight GND connection.
Use good signal integrity practices and follow AMD recommendations.
34
FN8322.0
December 19, 2012