ISL6277A Datasheet, PDF(30/38 Page) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0

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ISL6277A Datasheet, PDF (30/38 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0

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ISL6277A

immediately; then record the output voltage reading again when

the board has reached the thermal steady state. A good NTC

network can limit the output voltage drift to within 2mV. It is

recommended to follow the Intersil evaluation board layout and

current sensing network parameters to minimize engineering

time.

VCn(s) also needs to represent real-time Io(s) for the controller to

achieve good transient response. Transfer function Acs(s) has a

pole wsns and a zero wL. One needs to match wL and wsns so

Acs(s) is unity gain at all frequencies. By forcing wL equal to wsns

and solving for the solution, Equation 23 gives Cn value.

------------------------------L--------------------------------

-R----n---t--c---n----e---t---Ã------R--------s--N----u-------m------ Ã DCR

-R----s---u---m---

(EQ. 23)

For example, given N = 3, Rsum = 3.65kâ¦, Rp = 11kâ¦,

Rntcs = 2.61kâ¦, Rntc = 10kâ¦, DCR = 0.88mâ¦ and L = 0.36ÂµH,

Equation 23 gives Cn = 0.406ÂµF.

Assuming the compensator design is correct, Figure 23 shows the

expected load transient response waveforms if Cn is correctly

selected. When the load current Icore has a square change, the

output voltage Vcore also has a square response.

If Cn value is too large or too small, VCn(s) does not accurately

represent real-time Io(s) and worsens the transient response.

Figure 24 shows the load transient response when Cn is too

small. Vcore sags excessively upon load insertion and may create

a system failure. Figure 25 shows the transient response when

Cn is too large. Vcore is sluggish in drooping to its final value.

There is excessive overshoot if load insertion occurs during this

time, which may negatively affect the CPU reliability.

FIGURE 25. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE

RING

BACK

FIGURE 26. OUTPUT VOLTAGE RING-BACK PROBLEM

ISUM+

Rntcs

Rntc

Cn.1

OPTIONAL

Cn.2 Vcn

ISUM-

Rip Cip

FIGURE 23. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS

FIGURE 24. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL

OPTIONAL

FIGURE 27. OPTIONAL CIRCUITS FOR RING-BACK REDUCTION

Figure 26 shows the output voltage ring-back problem during load

transient response. The load current io has a fast step change, but

the inductor current iL cannot accurately follow. Instead, iL

responds in first-order system fashion due to the nature of the

current loop. The ESR and ESL effect of the output capacitors

makes the output voltage Vo dip quickly upon load current change.

However, the controller regulates Vo according to the droop current

idroop, which is a real-time representation of iL; therefore, it pulls

Vo back to the level dictated by iL, causing the ring-back problem.

This phenomenon is not observed when the output capacitor has

very low ESR and ESL, as is the case with all ceramic capacitors.

Figure 27 shows two optional circuits for reduction of the

ring-back. Cn is the capacitor used to match the inductor time

constant. It usually takes the parallel of two (or more) capacitors

to get the desired value. Figure 27 shows that two capacitors

(Cn.1 and Cn.2) are in parallel. Resistor Rn is an optional

component to reduce the Vo ring-back. At steady state, Cn.1 +

FN8322.0

December 19, 2012

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