ISL6267 Datasheet, PDF (30/33 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs

ISL6267
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ISL6267
TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER (Continued)
SYMBOL
LAYOUT GUIDELINES
ISUMN
ISUMP
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to VR1 phase-1 inductor (L1) so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two
signals traces in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route R63 and R71
to Core VR phase-1 side pad of inductor L1. Route R88 to the output side pad of inductor L1. Route R65 and
R72 to Core VR phase-2 side pad of inductor L2. Route R90 to the output side pad of inductor L2. If possible,
route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center
of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the
inductor. The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
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VDD
A capacitor (C16) decouples it to GND. Place it in close proximity to the controller.
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VIN
A capacitor (C17) decouples it to GND. Place it in close proximity to the controller.
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PROG1
No special consideration.
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BOOT1
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
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UGATE1
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE1 trace to VR1 phase-1 high-side MOSFET (Q2 and
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PHASE1
Q8) source pins instead of general copper.
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LGATE1
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
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PWM3
No special consideration.
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VCCP
A capacitor (C22) decouples it to GND. Place it in close proximity to the controller.
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LGATE2
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
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PHASE2
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE2 trace to VR1 phase-2 high-side MOSFET (Q4 and
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UGATE2
Q10) source pins instead of general copper.
35
BOOT2
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
36
PWM2_NB
No special consideration.
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LGATE1_NB
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
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PHASE1_NB Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE1G trace to VR2 phase-1 high-side MOSFET source
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UGATE1_NB
pins instead of general copper.
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BOOT1_NB
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
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PROG2
No special consideration.
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NTC_NB
Place the NTC thermistor close to the thermal source that is monitored to determine GT V_CORE thermal
throttling. Usually it is placed close to Northbridge VR phase-1 high-side MOSFET.
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ISUMN_NB
Place the current sensing circuit in general proximity to the controller.
Place capacitor Cn very close to the controller.
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ISUMP_NB
Place the NTC thermistor next to Northbridge VR phase-1 inductor (L1) so it senses the inductor temperature
correctly.
See ISUMN and ISUMP pins for layout guidelines of current-sensing trace routing.
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January 31, 2011
FN7801.0