ISL6267 Datasheet, PDF (15/33 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs

VCRM
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
PWM2
CLOCK3
PWM3
VW
COMP
VW
ISL6267
PHASE
UGATE
LGATE
IL
V_CRS
FIGURE 10. DIODE EMULATION
CCM/DCM
VW ^BOUNDARY
VCRS1
VCRS3
VCRS2
FIGURE 9. R³â„¢ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
Diode Emulation and Period Stretching
The ISL6267 can operate in diode emulation (DE) mode to
improve light-load efficiency. In DE mode, the low-side MOSFET
conducts when the current is flowing from source to drain and
does not allow reverse current, thus emulating a diode. As Figure
10 shows, when LGATE is on, the low-side MOSFET carries current,
creating negative voltage on the phase node due to the voltage
drop across the ON-resistance. The ISL6267 monitors the current
by monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary power loss.
If the load current is light enough, as Figure 10 shows, the
inductor current reaches and stays at zero before the next phase
node pulse, and the regulator is in discontinuous conduction
mode (DCM). If the load current is heavy enough, the inductor
current will never reaches 0A, and the regulator is in CCM,
although the controller is in DE mode.
Figure 11 shows the operation principle in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size and therefore is the same, making the inductor
current triangle the same in the three cases. The ISL6267 clamps
the ripple capacitor voltage V_CRS in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit V_CRS,
naturally stretching the switching period. The inductor current
triangles move farther apart such that the inductor current
average value is equal to the load current. The reduced switching
frequency helps increase light-load efficiency.
IL
V_CRS
VW ^{LIGHT DCM}
IL
V_CRS
DEEP DCM
VW
IL
FIGURE 11. PERIOD STRETCHING
Start-up Timing
With the controller's V_DD and V_IN voltages above their POR
threshold, the start-up sequence begins when ENABLE exceeds the
logic high threshold. Figure 12 shows the typical start-up timing of
VR1 and VR2. The ISL6267 uses digital soft-start to ramp-up DAC
to the voltage programmed by the Metal VID. PGOOD is asserted
high and low at the end of the ramp up. Similar results occur if
ENABLE is tied to V_DD, with the soft-start sequence starting
800µs after V_DD crosses the POR threshold.
15
January 31, 2011
FN7801.0