ISL6267 Datasheet, PDF (19/33 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs

ISL6267
SVC
6 5 4 32 10
See Table 3
SVID
7 654 3 210
SVD
SLAVE ADDRESS PHASE
DATA PHASE
FIGURE 14. SEND BYTE EXAMPLE
SVI Bus Protocol
The AMD processor bus protocol is compliant with SMBus send
byte protocol for VID transactions (see Figure 14). During a send
byte transaction, the processor sends the start sequence
followed by the slave address of the VR for which the VID
command applies. The address byte must be configured
according to Table 3. The processor then sends the write bit. After
the write bit, if the ISL6267 receives a valid address byte, it
sends the acknowledge bit. The processor then sends the PSI-L
bit and VID bits during the data phase. The Serial VID 8-bit data
field encoding is outlined in Table 4. If ISL6267 receives a valid
8-bit code during the data phase, it sends the acknowledge bit.
Finally, the processor sends the stop sequence. After the
ISL6267 has detected the stop, it can then proceed with the
VID-on-the-fly transition.
TABLE 3. SVI SEND BYTE ADDRESS DESCRIPTION
BITS
DESCRIPTION
6:4 Always 110b
3 Reserved by AMD for future use
2 VDD1; if set, then the following data byte contains the VID for
VDD1 [Note: The ISL6267 does not support VDD1]
1 VDD0; if set, then the following data byte contains the VID for
VID0
0 VDDNB; if set then the following data byte contains the VID for
VIDNB
VR Offset Programming
A positive or negative offset is programmed for the Core VR using
a resistor to ground from the PROG1 pin and the Northbridge in a
similar manner from the PROG2 pin. Table 5 provides the resistor
value to select the desired output voltage offset
TABLE 5. PROGx PIN RESISTOR VALUE
RESISTOR VALUE
[Ω]
0
PROG1
V_{CORE OFFSET} [mV]
50
PROG1
VNB
OFFSET [mV]
50
590
1100
43.75
37.50
43.75
37.50
1690
31.25
31.25
2260
25.00
25.00
3160
18.75
18.75
4320
12.50
12.50
5620
6.25
6.25
6650
7870
0.00
-6.25
0.00
-6.25
9530
11500
-12.50
-18.75
-12.50
-18.75
14000
-25.00
-25.00
TABLE 4. SERIAL VID 8-BIT DATA FIELD ENCODING
BITS
DESCRIPTION
7 PSI_L:
=0 means the processor is at an optimal load for the regulators
to enter power-saving mode
=1 means the processor is not at an optimal load for the
regulators to enter power-saving mode
6:0 SVID[6:0] as defined in Table 2.
Operation
After the start-up sequence, the ISL6267 begins regulating the
Core and Northbridge output voltages to the pre-PWROK metal
VID programmed. The controller monitors SVI commands to
determine when to enter power-saving mode, implement
dynamic VID changes, and shut down individual outputs.
16500
18700
OPEN
-31.25
-37.50
-43.75
-31.25
-37.50
-43.75
Voltage Regulation and Load Line
Implementation
After the start sequence, the ISL6267 regulates the output voltage
to the value set by the VID information, per Table 2. The ISL6267
controls the no-load output voltage to an accuracy of ±0.5% over
the range of 0.75V to 1.55V. A differential amplifier allows
voltage sensing for precise voltage regulation at the
microprocessor die.
19
January 31, 2011
FN7801.0