ISL6267 Datasheet, PDF (14/33 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs

ISL6267
Theory of Operation
Multiphase R³â„¢ Modulator
The ISL6267 is a multiphase regulator implementing two voltage
regulators, VDD and VDDNB, on one chip controlled by AMD’s™
SVI1™ protocol. VDD can be programmed for 1-, 2- or 3-phase
operation. VDDNB can be configured for 1- or 2-phase operation.
Both regulators use the Intersil patented R³â„¢ (Robust Ripple
Regulator) modulator. The R³â„¢ modulator combines the best
features of fixed frequency PWM and hysteretic PWM while
eliminating many of their shortcomings. Figure 7 conceptually
shows the multiphase R³â„¢ modulator circuit, and Figure 8 shows
the operation principles.
VW
MASTER CLOCK CIRCUIT
MASTER
MASTER
COMP
CLOCK _VCRM
CLOCK
PHASE
SEQUENCER
GMVO
CRM
CLOCK1
CLOCK2
CLOCK3
VW
VCRS1
CRS1
VW
VCRS2
CRS2
VW
VCRS3
CRS3
SLAVE CIRCUIT 1
CLOCK1 S PWM1 ^{PHASE1 L1}
Q
R
IL1
GM
SLAVE CIRCUIT 2
CLOCK2 S PWM2 ^{PHASE2 L2}
Q
R
IL2
GM
SLAVE CIRCUIT 3
CLOCK3 S PWM3 ^{PHASE3 L3}
Q
R
IL3
GM
VO
CO
FIGURE 7. R³â„¢ MODULATOR CIRCUIT
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called “VW window” in the following
discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C_rm with a current source equal
to g_mV_o, where g_m is a gain factor. C_rm voltage V_CRM is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If V_DD is in 3-phase
mode, the master clock signal is distributed to the three phases,
and the Clock 1~3 signals will be 120° out-of-phase. If VR1 is in
2-phase mode, the master clock signal is distributed to Phases 1
and 2, and the Clock1 and Clock2 signals will be 180° out-of-
phase. If VR1 is in 1-phase mode, the master clock signal will be
distributed to Phase 1 only and be the Clock1 signal.
VW
VCRM
COMP
HYSTERETIC
W IN D O W
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
PWM2
CLOCK3
PWM3
VW
VCRS2 VCRS3 VCRS1
FIGURE 8. R³â„¢ MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
Each slave circuit has its own ripple capacitor C_rs, whose voltage
mimics the inductor ripple current. A g_m amplifier converts the
inductor voltage into a current source to charge and discharge
C_rs. The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C_rs. When C_rs
voltage V_Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C_rs.
Since the controller works with V_crs, which are large amplitude
and noise-free synthesized signals, it achieves lower phase jitter
than conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode converters, the
error amplifier allows the ISL6267 to maintain a 0.5% output
voltage accuracy.
Figure 9 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency. This allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the COMP voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the ISL6267 excellent response
speed.
The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
14
January 31, 2011
FN7801.0