ISL6267 Datasheet, PDF (27/33 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion Mobile CPUs

ISL6267
Load Line Slope
See Figure 15 for load-line implementation.
For inductor DCR sensing, substitution of Equation 28 into
Equation 2 gives the load-line slope expression:
LL = -^V---^d---^r--^o----^o---^p- = -²---^R-----^d---^r--^o---^o---^p-- × -----------^R----ⁿ----^t--^c--ⁿ----^e---^t----------- × ^D-----^C----^R--
I_o
R_i
R_n
t
c
net
+
R_{-----s--u----m---}
N
N
(EQ. 35)
For resistor sensing, substitution of Equation 32 into Equation 2
gives the load line slope expression:
LL
=
-^V---^d---^r--^o----^o---^p-
I_o
=
-²---^R-----^s--^e----ⁿ----^×-----^R----^d---^r--^o---^o----^p-
N × R_i
(EQ. 36)
Substitution of Equation 29 and rewriting Equation 35, or
substitution of Equation 33 and rewriting Equation 36, gives the
same result as in Equation 37:
R_droop
=
------^I--^o------- × LL
I_droop
(EQ. 37)
One can use the full-load condition to calculate R_droop. For
example, given I_omax = 51A, I_droopmax = 40.9µA and
LL = 1.9mΩ, Equation 37 gives R_droop = 2.37kΩ.
It is recommended to start with the R_droop value calculated by
Equation 37 and fine-tune it on the actual board to get accurate
load-line slope. One should record the output voltage readings at
no load and at full load for load-line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.
Compensator
Figure 21 shows the desired load transient response waveforms.
Figure 27 shows the equivalent circuit of a voltage regulator (VR)
with the droop function. A VR is equivalent to a voltage source
(= VID) and output impedance Z_out(s). If Z_out(s) is equal to the
load-line slope LL, i.e., a constant output impedance, then in the
entire frequency range, V_o will have a square response when I_o
has a square change.
Zout(s) = LL
io
current, multiplies it by a gain of the load-line slope, adds it on top
of the sensed output voltage, and then feeds it to the
compensator. T1 is measured after the summing node, and T2 is
measured in the voltage loop before the summing node. The
spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)
can actually be measured on an ISL6267 regulator.
Q1
VIN
GATE Q2
DRIVER
L
VO
COUT
iO
LOAD LINE SLOPE
2_Ω0
MOD.
EA ^-
COMP
+
VID
CHANNEL B
LOOP GAIN = _{CHANNEL A}
+
+
ISOLATION
TRANSFORMER
CHANNEL A
NETWORK
ANALYZER
EXCITATION OUTPUT
CHANNEL B
FIGURE 28. LOOP GAIN T1(s) MEASUREMENT SET-UP
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s), therefore
has a higher impact on system stability.
T2(s) is the voltage loop gain with closed droop loop, thus having
a higher impact on output voltage response.
Design the compensator to get stable T1(s) and T2(s) with sufficient
phase margin and an output impedance equal to or smaller than
the load-line slope.
Q1
VIN
GATE Q2
DRIVER
L
VO
CO
IO
VID
VR
LOAD ^Vo
FIGURE 27. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
Intersil provides a Microsoft Excel-based spreadsheet to help
design the compensator and the current sensing network so that
VR achieves constant output impedance as a stable system.
Figure 29 shows a screenshot of the spreadsheet.
A VR with active droop function is a dual-loop system consisting of
a voltage loop and a droop loop, which is a current loop. However,
neither loop alone is sufficient to describe the entire system. The
spreadsheet shows two loop gain transfer functions, T1(s) and
T2(s), that describe the entire system. Figure 28 conceptually
shows T1(s) measurement set-up, and Figure 29 conceptually
shows T2(s) measurement set-up. The VR senses the inductor
LOAD LINE SLOPE
MOD.
COMP
-
EA
+
VID
CHANNEL B
LOOP GAIN =
CHANNEL A
++ ₂₀ Ω
ISOLATION
TRANSFORMER
CHANNEL A
NETWORK
ANALYZER
CHANNEL B
EXCITATION OUTPUT
FIGURE 29. LOOP GAIN T2(s) MEASUREMENT SET-UP
Current Balancing
Refer to Figures 16 through 20 for information on current
balancing. The ISL6267 achieves current balancing through
matching the ISEN pin voltages. R_isen and C_isen form filters to
remove the switching ripple of the phase node voltages. It is
27
January 31, 2011
FN7801.0