ISL62875 Datasheet, PDF (20/22 Pages) Intersil Corporation – PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator

ISL62875
FB, SREF, SET0, SET1, AND SET2 PINS
The input impedance of these pins is high, making it
critical to place the loop compensation components,
setpoint reference programming resistors, feedback
voltage divider resistors, and CSOFT close to the IC,
keeping the length of the traces short.
LGATE, PGND, UGATE, BOOT, AND PHASE PINS
The signals going through these traces are boht high
dv/dt and di/dt, with high peak charging and discharging
current. The PGND pin can only flow current from the
gate-source charge of the low-side MOSFETs when
LGATE goes low. Ideally, route the trace from the LGATE
pin in parallel with the trace from the PGND pin, route
the trace from the UGATE pin in parallel with the trace
from the PHASE pin, and route the trace from the BOOT
pin in parallel with the trace from the PHASE pin. These
pairs of traces should be short, wide, and away from
other traces with high input impedance; weak signal
traces should not be in proximity with these traces on
any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing.
It is best to limit the size of the PHASE node copper in
strict accordance with the current and thermal
management of the application. An MLCC should be
connected directly across the drain of the upper MOSFET
and the source of the lower MOSFET to suppress the
turn-off voltage.
20
September 18, 2009
FN6905.1