ISL62875 Datasheet, PDF (19/22 Pages) Intersil Corporation – PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator

ISL62875
- t_OFF is the time required to drive the device into
cut-off
PCB Layout Considerations
Power and Signal Layers Placement on the
PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with the weak
analog or logic signal layers on the opposite side of the
board. The ground-plane layer should be adjacent to the
signal layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the SREF components.
The island should be connected to the rest of the ground
plane layer at one point.
Component Placement
There are two sets of critical components in a DC/DC
converter; the power components and the small signal
components. The power components are the most critical
because they switch large amount of energy. The small
signal components connect to sensitive nodes or supply
critical bypassing current and signal coupling.
The power components should be placed first and these
include MOSFETs, input and output capacitors, and the
inductor. Keeping the distance between the power train
and the control IC short helps keep the gate drive traces
short. These drive signals include the LGATE, UGATE,
PGND, PHASE and BOOT.
When placing MOSFETs, try to keep the source of the
upper MOSFETs and the drain of the lower MOSFETs as
close as thermally possible (see Figure 13). Input high-
frequency capacitors should be placed close to the drain
of the upper MOSFETs and the source of the lower
MOSFETs. Place the output inductor and output
capacitors between the MOSFETs and the load. High-
frequency output decoupling capacitors (ceramic) should
be placed as close as possible to the decoupling target
(GPUor CPU), making use of the shortest connection
paths to any internal planes. Place the components in
such a way that the area under the IC has less noise
traces with high dV/dt and di/dt, such as gate signals and
phase node signals.
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
GND
VOUT
PHASE
NODE
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
VIN
CAPACITORS
FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT
Signal Ground and Power Ground
The GND pin is the signal-common also known as analog
ground of the IC. When laying out the PCB, it is very
important that the connection of the GND pin to the
bottom setpoint-reference programming-resistor, bottom
feedback voltage-divider resistor (if used), and the
CSOFT capacitor be made as close as possible to the
GND pin on a conductor not shared by any other
components.
In addition to the critical single point connection
discussed in the previous paragraph, the ground plane
layer of the PCB should have a single-point-connected
island located under the area encompassing the IC,
setpoint reference programming components, feedback
voltage divider components, compensation components,
CSOFT capacitor, and the interconnecting traces among
the components and the IC. The island should be
connected using several filled vias to the rest of the
ground plane layer at one point that is not in the path of
either large static currents or high di/dt currents. The
single connection point should also be where the VCC
decoupling capacitor and the GND pin of the IC are
connected.
Anywhere not within the analog-ground island is Power
Ground. Connect the input capacitor(s), the output
capacitor(s), and the source of the lower MOSFET(s) to
the power ground plane.
Routing and Connection Details
Specific pins (and the trace routing from them), require
extra attention during the layout process. The following
sub-sections outline concerns by pin name.
VCC PIN
For best performance, place the decoupling capacitor
next to the VCC and GND pins. The VCC decoupling
capacitor should not share any vias with the PVCC
decoupling capacitor.
PVCC PIN
For best performance, place the PVCC decoupling
capacitor next to the PVCC and PGND pins, preferably on
the same side of the PCB as the ISL62875. The PVCC
decoupling capacitor should have a very short and wide
trace connection to the PGND pin.
EN, PGOOD, VID0, AND VID1 PINS
These are logic signals that are referenced to the GND
pin. Treat as a typical logic signal.
OCSET AND VO PINS
The current-sensing network consisting of R_OCSET, R_O,
and C_SEN must be connnected to the inductor pads for
accurate measurement of the DCR voltage drop. These
components however, should be located physically close
to the OCSET and VO pins with traces leading back to the
inductor. It is critical that the traces are shielded by the
ground plane layer all the way to the inductor pads. The
procedure is the same for resistive current sense.
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September 18, 2009
FN6905.1