ISL62875 Datasheet, PDF (16/22 Pages) Intersil Corporation – PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator

ISL62875
Figure 9 shows the overcurrent set circuit. The inductor
consists of inductance L and the DC resistance DCR. The
inductor DC current I_L creates a voltage drop across
DCR, which is given by Equation 21:
V_DCR = I_L ⋅ DCR
(EQ. 21)
The I_OCSET current source sinks 10µA into the OCSET
pin, creating a DC voltage drop across the resistor
R_OCSET, which is given by Equation 22:
V_ROCSET = 10μA ⋅ R_OCSET
(EQ. 22)
The DC voltage difference between the OCSET pin and
the VO pin, which is given by Equation 23:
V_OCSET– V_VO = V_DCR– V_ROCSET =I_L ⋅DCR – I_OCSET⋅ R_OCSET
(EQ. 23)
The IC monitors the voltage of the OCSET pin and the VO
pin. When the voltage of the OCSET pin is higher than
the voltage of the VO pin for more than 10µs, an OCP
fault latches the converter off.
Component Selection for R_OCSET and C_SEN
The value of R_OCSET is calculated with Equation 24,
which is written as:
R_OCSET
=
I_{--O-----C-----}⋅_---D_-----C_-----R_---
I_OCSET
(EQ. 24)
Where:
- R_OCSET (Ω) is the resistor used to program the
overcurrent setpoint
- I_OC is the output DC load current that will activate
the OCP fault detection circuit
- DCR is the inductor DC resistance
For example, if I_OC is 20A and DCR is 4.5mΩ, the choice
of R_OCSET is = 20A x 4.5mΩ/10µA = 9kΩ.
Resistor R_OCSET and capacitor C_SEN form an R-C
network to sense the inductor current. To sense the
inductor current correctly not only in DC operation, but
also during dynamic operation, the R-C network time
constant R_OCSET C_SEN needs to match the inductor time
constant L/DCR. The value of C_SEN is then written as
Equation 25:
C_SEN
=
--------------------^L----------------------
R_OCSET ⋅ DCR
(EQ. 25)
For example, if L is 1.5µH, DCR is 4.5mΩ, and R_OCSET is
9kΩ, the choice of C_SEN = 1.5µH/(9kΩ x 4.5mΩ) =
0.037µF.
When an OCP fault is declared, the PGOOD pin will
pull-down to 35Ω and latch off the converter. The fault
will remain latched until the EN pin has been pulled below
the falling EN threshold voltage V_ENTHF or if VCC has
decayed below the falling POR threshold voltage
V_{VCC_THF.}
Overvoltage
The ISL62875 does not feature overvoltage fault
protection.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V_UVTH for
more than 2µs. For example, if the converter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to fall below the typical V_UVTH threshold of
84% for more than 2µs in order to trip the UVP fault
latch. In numerical terms, that would be
84% x 1.0V = 0.84V. When a UVP fault is declared, the
PGOOD pin will pull-down to 95Ω and latch-off the
converter. The fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
V_ENTHF or if VCC
threshold voltage
has decayed
V_{VCC_THF.}
below
the
falling
POR
Over-Temperature
When the temperature of the IC increases above the
rising threshold temperature T_OTRTH, it will enter the OTP
state that suspends the PWM, forcing the LGATE and
UGATE gate-driver outputs low. The status of the PGOOD
pin does not change nor does the converter latch-off. The
PWM remains suspended until the IC temperature falls
below the hysteresis temperature T_OTHYS at which time
normal PWM operation resumes. The OTP state can be
reset if the EN pin is pulled below the falling EN threshold
voltage V_ENTHF or if VCC has decayed below the falling
POR threshold voltage ^V_{VCC_THF}. All other protection
circuits remain functional while the IC is in the OTP state.
It is likely that the IC will detect an UVP fault because in
the absence of PWM, the output voltage decays below
the undervoltage threshold V_UVTH.
General Application Design
Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-
phase power converter. It is assumed that the reader is
familiar with many of the basic skills and techniques
referenced in the following. In addition to this guide,
Intersil provides complete reference designs that
include schematics, bills of materials, and example
board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of
the input and the output voltage. This relationship is
expressed in Equation 26:
D
=
-^V-----^O---
V_IN
(EQ. 26)
The output inductor peak-to-peak ripple current is
expressed in Equation 27:
I_P-P
=
-^V----^O-----^â‹---⁽---¹-----–----^D-----⁾
F_SW ⋅ L
(EQ. 27)
16
September 18, 2009
FN6905.1