ISL68137_16 Datasheet, PDF (18/53 Pages) Intersil Corporation – Digital Dual Output, 7-Phase Configurable PWM

ISL68137
Power-Good Signals
The PG0/PG1 pins are open-drain power-good outputs that
indicate completion of the soft-start sequence and output voltage
of the associated rail within the expected regulation range.
The PG pins may be associated or disassociated with a number of
the available fault types. This allows a system design to be tailored
for virtually any condition. In addition, these power-good
indicators will be pulled low when a fault (OCP or OVP) condition
or UV condition is detected on the associated rail.
Output Voltage Protection
Output voltage is measured at the load sensing points
differentially for regulation and the same measurement is used
for OVP and UVP. The fault thresholds are set using PMBus
commands. Figure 18 shows a simplified OVP/UVP block
diagram. The output voltage comparisons are done in the digital
domain.
VSENx ^ISL68137
RGNDx
ADC
THRESHOLD
REGISTER
DIGITAL OV
COMPARATOR
+
-
SoC
THRESHOLD
REGISTER
-
+
DIGITAL UV
COMPARATOR
FIGURE 18. OVP, UVP COMPARATORS
The device responds to an output overvoltage condition by
disabling the output, declaring a fault, setting the SALRT pin,
setting the PG pin and then pulsing the LFET until the output
voltage has dropped below the threshold. Similarly, the device
responds to an output undervoltage condition by disabling the
output, declaring a fault, setting the SALRT pin and setting the
PG pin. The output will not restart until the EN pin is cycled
(unless the device is configured to retry).
In addition, the ISL68137 features open pin sensing protection to
detect an open of the output voltage sensing circuit. When this
condition is detected, controller operation is suspended.
Output Current Protection
The ISL68137 offers a comprehensive overcurrent protection
scheme. Each phase is protected from both excessive peak
current and sustained current. In addition, the system is
protected from sustained total output overcurrent.
Figure 19 depicts a block diagram of the system total output
current protection scheme. In this scheme, the phase currents
are summed to form ISUM. ISUM is then fed to dual response
paths allowing the user to program separate LPF, threshold and
response time. One path is intended to allow response more
quickly than the other path. With this system, the user can allow
high peak total current for a short time and a lower level of
current for a sustained time. Note that neither of these paths
affect PWM activity on a cycle-by-cycle basis. The characteristics
of each path are easily set in PowerNavigator™.
In addition to total output current, the ISL68137 provides an
individual phase peak current limit that will act on PWM in a
cycle-by-cycle manner. This means that if a phase current is
detected to exceed the OC threshold, the phase PWM signal will
be inverted to move current away from the threshold. In addition
to limiting positive or negative peak current on a cycle-by-cycle
basis, individual phase OC can be configured to limit current
indefinitely or to declare a fault after a programmable number of
consecutive OC cycles. This feature is useful for applications
where a fault shutdown of the system would not be acceptable
but some ability to limit phase currents is desired. Figures 22
and 23 on page 19 depict this operation. If configured for
indefinite current limit, the converter will act as a current source
and V_OUT will not remain at its regulation point. It should be
noted that in this case, V_OUT OV or UV protection action may
occur, which could shut the regulator down.
PH1 CURRENT
SYNTHESIZER
PHn
CURRENT
SYNTHESIZER
 ^ISUM
TOTAL OUTPUT CURRENT FAULT
FAST SUM OC
FILTER COMPARE
TIMER
ACT
FILTER LIMIT
TIMER
DELAY
TO
FAULT
BLOCK
SLOW SUM OC
FILTER COMPARE
TIMER
ACT
FILTER LIMIT
TIMER
DELAY
TO
FAULT
BLOCK
PHASE PEAK CURRENT LIMITING AND FAULT
IPHASEn
COMPARE
+PEAK
LIMIT
COMPARE
-PEAK
LIMIT
COUNT
fSW clk Switching
Period
Count
May be set
for indefinite
limiting but
no fault
assertion
OCCOUNT
POSITIVE PEAK
LIMITING
COUNT
fSW clk
Switching
Period
Count
May be set
for indefinite
limiting but
no fault
assertion
UCCOUNT
NEGATIVE PEAK
LIMITING
ACT
TO
FAULT
BLOCK
PULSE BY
PULSE
LIMIT
ACT
TO
FAULT
BLOCK
PULSE BY
PULSE
LIMIT
FIGURE 19. OCP FUNCTIONAL DIAGRAM
Submit Document Feedback ₁₈
FN8757.0
September 27, 2016