GDPXA255A0E400 Datasheet, PDF (9/40 Pages) Intel Corporation – Electrical, Mechanical, and Thermal Specification

Package Information
Some of the processor pins can be connected to multiple signals. The GAFRn_m registers
determine the signal connected to the pin. Some signals can go to multiple pins. The signal must be
routed to one pin only by using the GAFRn_m registers. Because this is true, some pins are listed
twice—once in each unit that can use the pin. Not all peripherals can be used simutaneously in one
design because different peripherals share the same pins.
Table 2. Processor Pin Types
Type
Function
IC
OC
OCZ
ICOCZ
IA
OA
IAOA
SUP
CMOS input
CMOS output
CMOS output, Hi-Z
CMOS bidirectional, Hi-Z
Analog Input
Analog output
Analog bidirectional
Supply pin (either VCC or VSS)
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)
Pin Name
Type
Signal Descriptions
Reset State
Memory Controller Pins
MA[25:0]
OCZ
Memory address bus. (output) Signals the address
requested for memory accesses.
Driven Low
MD[15:0]
ICOCZ ^{Memory data bus. (input/output) Lower 16 bits of the}
Hi-Z
data bus.
Memory data bus. (input/output) Used for 32-bit
MD[31:16]
ICOCZ _memories.
Hi-Z
nOE
OCZ
Memory output enable. (output) Connect to the output _{Driven High}
enables of memory devices to control data bus drivers.
nWE
OCZ
Memory write enable. (output) Connect to the write
enables of memory devices.
Driven High
nSDCS[3:0]
OCZ
SDRAM CS for banks 3 through 0. (output) Connect to
the chip select (CS) pins for SDRAM. For the PXA255
processor processor nSDCS0 can be Hi-Z, nSDCS1-3
cannot.
Driven High
DQM[3:0]
OCZ
SDRAM DQM for data bytes 3 through 0. (output)
Connect to the data output mask enables (DQM) for
SDRAM.
Driven Low
nSDRAS
OCZ
SDRAM RAS. (output) Connect to the row address
strobe (RAS) pins for all banks of SDRAM.
Driven High
nSDCAS
OCZ
SDRAM CAS. (output) Connect to the column address
strobe (CAS) pins for all banks of SDRAM.
Driven High
SDCKE[0]
Synchronous Static Memory clock enable. (output)
OC
Connect to the CKE pins of SMROM. The memory
Driven Low
controller provides control register bits for de-assertion.
Sleep State
Driven Low
Driven Low
Driven Low
Note [4]
Note [4]
Note [5]
Driven Low
Driven High
Driven High
Driven Low
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
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