GDPXA255A0E400 Datasheet, PDF (33/40 Pages) Intel Corporation – Electrical, Mechanical, and Thermal Specification

Electrical Specifications
Figure 5. GPIO Reset Timing
t
A_GP[1]
GP[1]
nRESET_OUT
t
DHW_OUT
t
DHW_OUT_A
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is
deasserted or the application processor will enter Sleep Mode
Table 17. GPIO Reset Timing Specifications
Symbol
Description
Min
Typical
Max
Units
Minimum assert time of GP[1]¹ in
tA_GP[1]
4
3.6864MHz input clock cycles
cycles
Delay between GP[1] asserted and
tDHW_OUT_A nRESET_OUT asserted in 3.6864 MHz
3
input clock cycles
8
cycles
tDHW_OUT
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, run or
turbo mode²
1.28
6.5
µs
Delay between nRESET_OUT asserted
tDHW_OUT_F and nRESET_OUT de-asserted, during
frequency change sequence³
1.28
360
µs
Delay between nReset_Out de-asserted
tDHW_NCS0 _{and nCS0 asserted}
150.69
—
390
ns
NOTES:
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should
check the state of GP[1] before configuring as a reset to ensure no spurious reset is generated.
2. Time is 512*N processor clock cycles plus up to 4 cycles of the 3.6864-MHz input clock.
3. Time during the frequency change sequence depends on the state of the PLL lock detector at the
assertion of GPIO reset. The lock detector has a maximum time of 350µs plus synchronization.
4.7.5
Sleep Mode Timing
Sleep mode is asserted internally; and asserts the nRESET_OUT and PWR_EN signals. The
sequence indicated in Figure 6, “Sleep Mode Timing” on page 34 and detailed in Figure 18, “Sleep
Mode Timing Specifications” on page 34 is the required timing parameters for sleep mode.
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
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