GDPXA255A0E400 Datasheet, PDF (8/40 Pages) Intel Corporation – Electrical, Mechanical, and Thermal Specification

Package Information
Figure 1. Processor Block Diagram
RTC
OS Timer
PWM(2)
Int.
Controller
Clocks &
Power Man.
I²S
I²C
AC97
UARTs
NSSP
Slow IrDA
Fast IrDA
SSP
USB
Client
MMC
Color or
Grayscale
LCD
Controller
Memory
Controller
System Bus
Intelfi XScale
Microarchitecture
3.6864
MHz
Osc
32.768
KHz
Osc
Variable
Latency I/O
Control
PCMCIA
& CF
Control
Dynamic
Memory
Control
Static
Memory
Control
ASIC
XCVR
Socket 0
Socket 1
SDRAM/
SMROM
4 banks
ROM/
Flash/
SRAM
4 banks
3.0
Package Information
3.1
3.1.1
3.1.1.1
Package Introduction
The PXA255 processor is offered in a 256-pin mBGA (refer to Figure 2, “PXA255 processor” on
page 19).
Functional Signal Definitions
PXA255 Processor Signal Pin Descriptions
Table 3, “Pin and Signal Descriptions for the PXA255 Processor” on page 9 describes the signal
definitions for the PXA255 processor. Figure 2, “PXA255 processor” on page 19 illustrates the
physical characteristics of the PXA255 processor. Table 5, “PXA255 processor 256-Lead
17x17mm mBGA Pinout — Ballpad No. Order” on page 20 describes the pinout for the PXA255
processor.
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Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification