GDPXA255A0E400 Datasheet, PDF (31/40 Pages) Intel Corporation – Electrical, Mechanical, and Thermal Specification

Electrical Specifications
Note: If hardware reset is entered during sleep mode, follow the proper power-supply stabilization times
indicated in Figure 3 and nRESET timing requirements indicated in Table 15.
Figure 3. Power-On Reset Timing
t_{R_VCCQ}
VCCQ, PWR_EN
VCCN
VCC
nTRST
t_{R_VCCN}
t_{D_VCCN}
t_{R_VCC}
t_{D_VCC}
t_{D_NTRST}
JTAG PINS
t_{D_JTAG}
nRESET
t_{D_NRESET}
nRESET_OUT
t_{D_OUT}
NOTES:
1. nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is deasserted or the
processor enters sleep mode.
2. The inclusion of PWR_EN is for informational purposes only to show its relationship to VCCQ. The
use of PWR_EN to bring up VCCN or VCC at power-on reset is optional depending on the system’s
power management requirements. VCCN and VCC are not dependant on the PWR_EN signal being
asserted.
Table 15. Power-On Timing Specifications
Symbol
Description
Min
tR_VCCQ VCCQ rise / stabilization time
tR_VCCN VCCN rise / stabilization time
tR_VCC VCC, PLL_VCC rise / stabilization time
tD_VCCN ^{Delay between VCCQ applied and}
VCCN applied
tD_VCC
Delay from VCCN applied and VCC,
PLL_VCC applied
Delay between VCC, PLL_VCC stable
tD_NTRST _{and nTRST de-asserted}
tD_JTAG
Delay between nTRST de-asserted and
JTAG pins active, with nRESET
asserted
tD_NRESET
Delay between VCC, PLL_VCC stable
and nRESET de-asserted
tD_OUT
Delay between nRESET de-asserted
and nRESET_OUT de--asserted
tD_NCS0 ^{Delay between nRESET_OUT}
deasserted and nCS0 asserted
0.01
0.01
0.01
0
-10
10
0.03
10
18.1
400
Typical
—
—
—
—
—
—
—
—
—
—
Max
Units
100
ms
100
ms
10
ms
—
ms
—
ms
—
ms
—
ms
—
ms
18.2
ms
420
ns
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
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