GDPXA255A0E400 Datasheet, PDF (34/40 Pages) Intel Corporation – Electrical, Mechanical, and Thermal Specification

Electrical Specifications
Figure 6. Sleep Mode Timing
t
A_GP[x]
GP[x]
PWR_EN
t
D_PWR_F
t
D_PWR_R
t
DSM_VCC
VCC
nVDD_FAULT
t
D_F A UL T
nRESET_OUT
t
DSM_OUT
Not_e:_: nBAT_TT_FA_AUL_{T m}m_ust be_e h_hi_ig_gh_h o_or_r C_tho_etu_Pl_Xla_Aw₂i₅ll₅n_po_rt_oe_cx_eit_ssS_ole_rep Mode
will not exit sleep mode.
Table 18. Sleep Mode Timing Specifications
Symbol
Description
Min
Typical
Max
Units
tA_GP[x} ^{Assert time of GPIO wake-up source}
91.6
—
(x=[15:0])
—
µs
Delay from nRESET_OUT asserted to
tD_PWR_F _{PWR_EN de-asserted}
61
—
91.6
µs
Delay between GP[x] asserted to
tD_PWR_R _{PWR_EN asserted}
30.5
—
122.1
µs
tDSM_VCC ^{Delay between PWR_EN asserted and}
VCC stable
—
10
ms
Delay between PWR_EN asserted and
tD_FAULT _{nVDD_FAULT de-asserted}
—
10
ms
Delay between PWR_EN asserted and
tDSM_OUT _{nRESET_OUT de-asserted, OPDE set}
28.0
—
28.5
ms
tDSM_OUT_F ^{Delay between PWR_EN asserted and}
—
nRESET_OUT de-asserted, FWAKE set
—
650
µs
Delay between PWR_EN asserted and
tDSM_OUT_O nRESET_OUT de-asserted, OPDE
10.35
—
10.5
ms
clear
Delay between nReset_Out de-asserted
t_{DSM_NCS0 and nCS0 asserted}
180.84
—
332
ns
NOTE: For the parameter t_{DSM_VCC}, VCC refers to the VCC supply internal to the processor. The internal
VCC regulator must be stable within the stated maximum for the processor to function correctly.
Factors such as external voltage regulator ramp time and bulk capacitance will affect the ramp time of
the internal regulator and must be taken into account when designing the system.
34
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification