GDPXA255A0E400 Datasheet, PDF (17/40 Pages) Intel Corporation – Electrical, Mechanical, and Thermal Specification

Package Information
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)
Pin Name
Type
Signal Descriptions
Reset State
Sleep State
nRESET_OUT OC
JTAG and Test Pins
nTRST
IC
TDI
IC
TDO
OCZ
TMS
IC
TCK
IC
TEST
IC
TESTCLK
IC
Power and Ground Pins
VCC
SUP
VSS
SUP
PLL_VCC
SUP
PLL_VSS
SUP
VCCQ
SUP
VSSQ
SUP
VCCN
SUP
VSSN
SUP
Reset out. (output) Asserted when nRESET is asserted
and deasserts after nRESET is de-asserted but before
the first instruction fetch. nRESET_OUT is also asserted
for “soft” reset events: sleep, watchdog reset, or GPIO
reset.
Driven low during
any reset sequence
- driven high prior to
first fetch.
Driven Low
JTAG test interface reset. Resets the JTAG/debug port.
If JTAG/debug is used, drive nTRST from low to high
either before or at the same time as nRESET. If JTAG is
not used, nTRST must be either tied to nRESET or tied
low.
Input
JTAG test data input. (input) Data from the JTAG
controller is sent to the PXA255 processor using this pin. Input
This pin has an internal pull-up resistor.
JTAG test data output. (output) Data from the PXA255
processor is returned to the JTAG controller using this Hi-Z
pin.
JTAG test mode select. (input) Selects the test mode
required from the JTAG controller. This pin has an
internal pull-up resistor.
Input
JTAG test clock. (input) Clock for all transfers on the
JTAG test interface.
Input
Test Mode. (input) Reserved. Must be grounded.
Input
Test Clock. (input) Reserved. Must be grounded.
Input
Input
Input
Hi-Z
Input
Input
Input
Input
Positive supply for internal logic. Must be connected _Powered
to the low voltage supply on the PCB.
Ground supply for internal logic. Must be connected to
the common ground plane on the PCB.
Grounded
Positive supply for PLLs and oscillators. Must be
connected to the common low voltage supply.
Powered
Ground supply for the PLL. Must be connected to
common ground plane on the PCB.
Grounded
Positive supply for all CMOS I/O except memory bus
and PCMCIA pins. Must be connected to the common Powered
3.3v supply on the PCB.
Ground supply for all CMOS I/O except memory bus
and PCMCIA pins. Must be connected to the common
ground plane on the PCB.
Grounded
Positive supply for memory bus and PCMCIA pins.
Must be connected to the common 3.3v or 2.5v supply on Powered
the PCB.
Ground supply for memory bus and PCMCIA pins.
Must be connected to the common ground plane on the
PCB.
Grounded
Note [6]
Grounded
Note [6]
Grounded
Note [7]
Grounded
Note [7]
Grounded
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
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