82802AB Datasheet, PDF (9/53 Pages) Intel Corporation – Firmware Hub (FWH)

Intel^® 82802AB/AC Firmware Hub
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1. Architectural Overview
The Intel^® 82802 Firmware Hub (FWH) discrete component is compatible with several Intel chipset
platforms and a variety of applications. The device operates under the LPC/FWH interface/protocol. The
hardware features of this device include a Random Number Generator (RNG), five General-Purpose
Inputs (GPIs), register-based block locking, and hardware-based locking. This combination of logic
features and non-volatile memory enables better protection for the storage and update of platform code
and data, adds platform flexibility through additional GPIs, and allows for quicker introduction of new
security/manageability features into current and future platforms. The platform RNG, accessed through
the Intel^® Security Driver and third-party software, enables security features for the PC platform. See the
product features listed previously for a list of more key features that the Intel FWH provides.
1.1. Interface Overview
This device is equipped with two hardware interfaces. The state of the device’s “IC”
(InterfaceConfiguration) pin determines which interface is in use. The interface mode must be selected
prior topower-up or before return from reset (RST# or INIT# low-to-high transition). The Intel FWH
interface isdesigned to work with the Intel family of I/O Controller Hubs (ICH) during platform
operation. The A/A Mux interface is designed as a programming interface for OEMs, for use during
motherboard manufacturing or component pre-programming. The A/A Mux interface is not intended for
use during regular personal computer operation. Such a configuration would cause the expected (Intel
FWH) interface to be disabled, and the system boot sequence would fail upon power-up.
An internal Command User Interface (CUI) serves as the internal control center for the
nonvolatilememory core in either of the two device interfaces (Intel FWH or A/A Mux). A single valid
commandsequence written to the CUI initiates an automated sequence of internal events to complete
various tasks. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase and program operations.
Driving RST# or INIT# low resets the device, which resets the block-lock registers to their default
(write-locked) condition and clears the status register. A reset time (tPHQV A/A Mux) is required from
RST# or INIT# switching high until outputs are valid. Likewise, the device has a wake time (tPHRH A/A
Mux) from RST# or INIT# high until writes to the CUI are recognized. A reset latency will occur if a
reset procedure is performed during a programming or erase operation. Resetting the component will put
the component back into read-array mode.
Note: There is no chip enable (like CE#) in either interface. Stand-by current control in the Inel FWH interface
is enabled automatically, if the Intel FWH4 is high and the device is not working to complete a requested
activity.
Datasheet
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