82802AB Datasheet, PDF (40/53 Pages) Intel Corporation – Firmware Hub (FWH)

Intel^® 82802AB/AC Firmware Hub
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5.3. Block Programming Times
Table 15. Programming Times
Parameter
Byte program time
Block program time
Block erase time
Notes
2
2
2
3.3 V VPP
Typ.⁽¹⁾ Max.
17
300
1.1
4.0
0.8
6.0
12 V VPP
Typ.⁽¹⁾ Max.
7.0
125
0.5
1.5
0.3
4.0
Unit
µs
sec
sec
Note:
1. Typical values measured at TA = +25°C and nominal voltages.
2. Excludes system-level overhead.
5.4.
Intel Firmware Hub Interface
The firmware hub relies on the Intel Firmware Hub interface to communicate with the outside world.
This interface consists of four bi-directional signals and one “control” input. The timing and electrical
parameters of the FWH interface are similar to those of the LPC interface, to provide compatibility
between the interfaces, but differ in cases mentioned earlier in this section (clock pin capacitance), as
well as in certain timing parameters. The Intel ICH has been engineered to accommodate both interfaces,
which allows the Intel FWH interface signals to be communicated over the same set of pins as LPC. The
Intel FWH interface is designed to use an LPC-compatible start cycle, with a reserved cycle type code.
This ensures that all LPC devices present on the shared interface will ignore cycles destined for the
FWH, without becoming “confused” by the different protocol.
This section contains timing and protocol information for the Intel FWH interface. Note that the Intel
FWH interface is a licensed interface, so the appropriate license must be obtained from Intel for
components supporting the Intel FWH interface (e.g., ASICs, PLDs).
5.4.1.
5.4.1.1.
Intel FWH Interface Cycles
When the Intel FWH interface is active, information is transferred to and from the FWH by a series of
“fields,” where each field contains 4 bits of data. Many fields are one clock cycle in length but can be of
variable length, depending upon the nature of the field. Field sequences and contents are strictly defined
for read and write operations. The following tables list the field sequences for read and write cycles.
Addresses in this section refer to addresses as seen from the FWH’s “point of view,” so some calculation
will be required to translate these to the actual locations in the memory map (and vice versa).
Read Cycle Sequence
The firmware hub supports single-byte or multibyte reads. The logic waveforms for these cycles are
shown in Table 16 and Figure 11
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Datasheet