82802AB Datasheet, PDF (41/53 Pages) Intel Corporation – Firmware Hub (FWH)

Intel^® 82802AB/AC Firmware Hub
R
Table 16. FWH Read Cycle
Clock
Cycle
1
Field
Name
START
2
IDSEL
3-9
IMADDR
10
IMSIZE
11
TAR0
12
TAR1
13-14 WSYNC
15
RSYNC
16
DATA
17
DATA
17+
3 x 2^n-1 +
2ⁿ
Previous
+1
“DATA”
TAR0
Previous
+1
TAR1
Field Contents¹
FWH[3:0]
1101
0000
to
1111
YYYY
0000 (1 byte)
1111
1111 (float)
0101 (WAIT)
0000 (READY)
YYYY
YYYY
2 WSYNCS +
1 RSYNC +
2 DATA
1111
1111 (float)
FWH[3:0]
Direction
Comments
IN
IN
IN
IN
IN
then float
Float then
OUT
OUT
OUT
OUT
OUT
OUT
OUT
then float
Float then
IN
FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitioning high)
should be recognized. The START field contents
indicate an FWH memory read cycle.
Indicates which FWH device should respond. If the
IDSEL (ID select) field matches the value ID[3:0], then
that particular device will respond to subsequent
commands.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
On multibyte data transfers, lower-order addresses will
be zero, depending on page size.
A field of this size indicates how many bytes will be
transferred during multibyte operations. The FWH will
only support single-byte transfers.
In this clock cycle, the master (Intel ICH) has driven the
bus to all 1s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle.”
The FWH takes control of the bus during this cycle.
During the next clock cycle, it will be driving “sync
data.”
The FWH outputs the value 0101, a wait-sync
(WSYNC, a.k.a. “short-sync”), for two clock cycles. This
value indicates to the master (Intel ICH) that data is not
yet available from the part. This number of wait-syncs
is a function of the device’s access time.
During this clock cycle, the FWH will generate a “ready-
sync” (RSYNC) indicating that the least-significant
nibble of the least-significant byte will be available
during the next clock cycle.
YYYY is the least-significant nibble of the least-
significant data byte.
YYYY is the most-significant nibble of the least-
significant data byte.
n = IMSIZE. Each subsequent byte of data requires 2
wait-syncs + 1 ready-sync + 2 data nibbles.
The FWH supports only n=0000 (single-byte) reads.
In this clock cycle, the Inel FWH has driven the bus to
all ones and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround cycle.”
The master (Intel ICH) resumes control of the bus
during this cycle.
Note:
1. Field contents are valid on the rising edge of the present clock cycle.
Datasheet
41