82802AB Datasheet, PDF (49/53 Pages) Intel Corporation – Firmware Hub (FWH)

Intel^® 82802AB/AC Firmware Hub
R
6.4.1. Reset Operations
# Symbol
Parameter
Notes
Min.
Max.
Unit
P1
tPLPH RST# pulse low time (If RST# is tied to VCC, this
100
ns
specification is not applicable.)
P2
tPLRH RST# low to reset during block erase or program
1, 2
20
µs
Note:
1. If RST# is asserted when the WSM is not busy (RY/BY# = ‘1’), the reset will complete within 100
ns.
2. A reset time, tPHAV, is required from the latter of RY/BY# or RST# going high until outputs are
valid.
6.4.2. AC Waveforms for Reset Operations
RY/BY# (R) ^VIH
V_IL
RST# (P) ^VIH
V_IL
P2
P1
6.4.3. A/A Mux Read-Only Operations ^(1,3)
#
Symbol
Parameter
R1
t_AVAV Read cycle time
R2
t_AVCL Row address setup to R/C# low
R3
t_CLAX Row address hold from R/C# low
R4
t_AVCH Column address setup to R/C# high
R5
t_CHAX Column address hold from R/C# high
R6
t_CHQV R/C# high to output delay
R7
t_GLQV OE# low to output delay
R8
t_PHAV RST# high to row address setup
R9
t_GLQX OE# low to output in low Z
R10
t_GHQZ OE# high to output in high Z
R11
t_QXGH Output hold from OE# high
Notes Min. Max. Unit
250
ns
50
ns
50
ns
50
ns
50
ns
2
150
ns
2
50
ns
1
µs
0
ns
50
ns
0
ns
Note:
1. See the AC input/output reference waveform for the maximum allowable input slew rate.
2. OE# may be delayed up to tCHQV – tGLQV after the rising edge of R/C# without affecting tCHQV.
3. Tc = 0 °C to + 85 °C, 3.3 V ± 0.3 V VCC
Datasheet
49