82802AB Datasheet, PDF (43/53 Pages) Intel Corporation – Firmware Hub (FWH)

Intel^® 82802AB/AC Firmware Hub
R
Clock
Cycle
16
17
Field
Name
TAR0
TAR1
Field Contents¹
FWH[3:0]
1111
1111 (float)
FWH[3:0]
Direction
OUT
then float
Float then
IN
Comments
In this clock cycle, the FWH has driven the bus to all
1s and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround
cycle.”
The master (Intel ICH) resumes control of the bus
during this cycle.
Note:
1. Field contents are valid on the rising edge of the present clock cycle.
5.4.1.4. Write Waveforms
Figure 11. Write Waveforms
CLK
FWH4
FWH[3:0]
STR IDS
IMADDR
IMS DATA
TAR SYN
C
TAR
5.4.1.5.
Response To Invalid Fields
During FWH operations, the Intel FWH will not explicitly indicate that it has received invalid field
sequences. The response to specific invalid fields or sequences is as follows:
• Address out of range: The Intel FWH address sequence is 7 fields long (28 bits), but only the last
five address fields (20 bits) will be decoded by an 8-Mbit FWH. (For a 4-Mbit density, the most-
significant bit (FWH3) in the third address field also will be ignored.) The Intel FWH will respond
to these lower addresses, regardless of the value of the more-significant address bits. Address A22
has the special function of directing reads and writes to the flash core (A22 = 1) or to the register
space (A22 = 0).
• Invalid IMSIZE field: If the Intel FWH receives an invalid size field during a read or write
operation, the internal state machine will reset and no operation will be attempted. The Intel FWH
will generate no response of any kind in this situation. Invalid-size fields for a read cycle are
anything but 0000. Invalid-size fields for a write cycle are anything but 0000. When accessing
register space, invalid field sizes are anything but 0000.
• Non-page-aligned address: The Intel FWH assumes that multibyte read addresses are page aligned
(i.e., for a 32-byte access, the lower 5 address bits will be zero). If they are not zero, the first byte
of data returned by the Intel FWH will correspond to that explicit address, and subsequent data will
be as if the first address was indeed page aligned.
Once valid START, IDSEL, and IMSIZE fields are received, the Intel FWH always will respond to
subsequent inputs as if they were valid. As long as the states of FWH [3:0] and FWH4 are known, the
response of the Intel FWH to signals received during the FWH cycle should be predictable. The Intel
FWH will make no attempt to check the validity of incoming flash operation commands.
Datasheet
43