82802AB Datasheet, PDF (15/53 Pages) Intel Corporation – Firmware Hub (FWH)

Intel^® 82802AB/AC Firmware Hub
R
Symbol Type
ID[3:0]
I
FGPI[4:0]
I
TBL#
I
WP#
I
A[0:10]
I
DQ[0:7]
I/O
OE#
I
R/C#
I
WE#
I
Interface
Name and Function
Intel
FWH
A/A Mux
X
Identification Inputs. These four pins are part of the mechanism
that allows multiple parts to be attached to the same bus. The
strapping of these pins is used to identify the component. The boot
device must have ID[3:0] = 0000, and it is recommended that all
subsequent devices use sequential up-count strapping (0001,
0010,0011,...). These pins are pulled down with internal resistors, with
values between 20 and 100 kΩ, when in the Intel FWH mode. Any
ID pins pulled high will exhibit a leakage current of approximately
200 µA. Any pins intended to be low may be left to float. In a single
Intel FWH system, all may be left floating.
A/A Mux = A[3:0]
Intel FWH General Purpose Inputs. These individual inputs can be
used for additional board flexibility. The state of these pins can be
read immediately at boot, through Intel FWH registers. These inputs
should be at their desired state before the start of the PCI clock
X
cycle during which the read is attempted, and they should remain at
the same level until the end of the read cycle. They may only be
used for 3.3-V signals. Unused FGPI pins must not be floated.
A/A Mux = A[10:6]
Top Block Lock. When low, it prevents programming or block erase
to the highest addressable block (7 in a 4-Mbit, 15 in an 8-Mbit
component), regardless of the state of the lock register. TBL#-high
X
disables hardware write protection for the top block, though register-
based protection still applies. The status of TBL# does not affect the
status of block-locking registers.
A/A Mux = A4
Write Protect. When low, prevents programming or block erase to
all but the highest addressable block (0-6 in a 4-Mbit, 0-14 in an 8-
Mbit component), regardless of the state of the corresponding lock
X
registers. WP#-high disables hardware write protection for these
blocks, though register-based protection still applies. The status of
TBL# does not affect the status of block-locking registers.
A/A Mux = A5
Low-Order Address Inputs. Inputs for low-order addresses during
X
read and write operations. Addresses are internally latched during a
write cycle. For the A/A Mux interface, these addresses are latched
by R/C# and share the same pins as the high-order address inputs.
Data Input/Outputs. These pins receive data and commands during
CUI write cycles and transmit data during memory array, status
X
register, and identifier code read cycles. Data pins float to high
impedance when outputs are disabled. Data is internally latched
during a write cycle.
X
Output Enable. Gates the device’s outputs during a read cycle
Row-Column Address Select. For the A/A Mux interface, this pin
X
determines whether the address pins are pointing to the row
addresses (A[0:10]) or the column addresses (A[11:19]).
Write Enable. Controls writes to the CUI and array blocks.
X
Addresses and data are latched on the rising edge of the WE#
pulse.
Datasheet
15