82802AB Datasheet, PDF (10/53 Pages) Intel Corporation – Firmware Hub (FWH)

Intel^® 82802AB/AC Firmware Hub
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Intel Firmware Hub Interface
The Intel Firmware Hub (Intel FWH) interface consists primarily of a 5-signal communication interface
used to control the operation of the device in a system environment. The buffers for this interface were
designed to be PCI compliant. To ensure the effective delivery of security and manageability features, the
Intel FWH interface is the only way access the full feature set of the device. The Intel FWH interface is
equipped to operate at 33 MHz, synchronous with the PCI bus.
Address/Address-Multiplexed Interface
The A/A Mux refers to the multiplexed row and column addresses in this interface. This approach is
required so that the device can be tested and programmed quickly with automated test equipment (ATE)
or off-board PROM programmers in the OEM’s manufacturing flow. This interface also allows the
device to have an efficient programming interface with potentially large future densities, while still fitting
into a 32-pin package. Only basic reads, programming, and erasure of the nonvolatile memory blocks can
be performed through the A/A Mux interface. In this mode, the Intel FWH features, security features, and
registers are unavailable. A row/column (R/C#) pin determines which set of addresses (rows or columns)
is latched. See the A/A Mux pin description table for more information.
Nonvolatile Flash Memory Core
The primary feature of the Intel FWH component is a nonvolatile memory core based on Intel^® Flash
Technology. This high-performance memory array is arranged in eight (4-Mbit device) or sixteen (8-
Mbit device) 64-KB blocks.
Intel^® Flash Technology enables fast factory programming and low-power designs. Specifically designed
for 3-V systems, this component supports read operations at 3.3 V VCC and block erase and program
operations at 3.3 V and 12 V VPP. The 12 V VPP option yields the fastest program performance, which
will increase factory throughput, but is not recommended for standard in-system FWH operation in the
platform, due to an 80-hr limit for 12 V on the VPP pin over the lifetime of the device, whether or not
programming is taking place. With the 3.3-V VPP option (recommended for in-system operation), VCC
and VPP may be tied together for a simple, low-power 3-V design. In addition to the voltage flexibility,
the dedicated VPP pin provides complete data protection when VPP ≤ VPPLK. Internal VPP detection
circuitry automatically configures the device for block erase and program operations. While current for
12-V programming will be drawn from V_PP, 3.3-V programming solutions should design their board such
that V_PP draws from the same supply as V_CC, and should assume that full programming current may be
drawn from either pin.
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Datasheet