82802AB Datasheet, PDF (42/53 Pages) Intel Corporation – Firmware Hub (FWH)

Intel^® 82802AB/AC Firmware Hub
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5.4.1.2. Single-Byte Read Waveforms
Figure 10. FWH Single-Byte Read Waveforms
CLK
FWH4
FWH[3:0]
STR IDS
IMADDR
IMS TAR
SYNC(3)
DATA
TAR
5.4.1.3. Write Cycle Sequence
The firmware hub only supports single-byte writes. Each byte represents either the data to be written or a
valid flash command. Refer to the waveforms in Figure 11.
Table 17. FWH Write Cycle
Clock
Cycle
1
Field
Name
START
Field Contents¹
FWH[3:0]
1110
2
IDSEL
3-9
IMADDR
0000
to
1111
YYYY
10
IMSIZE
0000 (1 byte)
11
DATA
YYYY
12
DATA
13
TAR0
YYYY
1111
14
TAR1
1111 (float)
15
RSYNC
0000
FWH[3:0]
Direction
IN
IN
IN
IN
IN
IN
IN
then float
Float then
OUT
OUT
Comments
FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitioning
high) should be recognized. The START field
contents indicate an FWH memory write cycle.
Indicates which FWH device should respond. If the
IDSEL (ID select) field matches the value ID[3:0],
then that particular device will respond to subsequent
commands.
These seven clock cycles make up the 28-bit
memory address. YYYY is one nibble of the entire
address. Addresses are transferred most-significant
nibble first.
This size field indicates how many bytes will be
transferred during read/write operations. The FWH
only supports single-byte writes.
This field is the least-significant nibble of the data
byte. This data is either the data to be programmed
into the flash memory or any valid flash command.
This field is the most-significant nibble of the data
byte.
In this clock cycle, the master (Intel ICH) has driven
the bus to all 1s and then floats the bus prior to the
next clock cycle. This is the first part of the bus
“turnaround cycle.”
The FWH takes control of the bus during this cycle.
During the next clock cycle it will be driving the “sync”
data.
The FWH outputs the values 0000, indicating that it
has received data or a flash command.
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Datasheet