82527 Datasheet, PDF (8/22 Pages) Intel Corporation – SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL

82527
A C Characteristics for 8 16-Bit Multiplexed Intel Modes (Modes 0 1)
Conditions V_CC ^e 5V g10% V_SS ^e 0V T_A ^{e b}40 C to ^a125 C C_L ^e 100 pF
Symbol
Parameter
Min
Max
1 t_XTAL
1 t_SCLK
1 t_MCLK
t_AVLL
t_LLAX
t_LHLL
t_LLRL
t_CLLL
t_QVWH
t_WHQX
t_WLWH
t_WHLH
t_WHCH
t_RLRH
t_RLDV
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to ALE Low
Address Hold after ALE Low
ALE High Time
ALE Low to RD Low
CS Low to ALE Low
Data Setup to WR High
Input Data Hold after WR High
WR Pulse Width
WR High to Next ALE High
WR High to CS High
RD Pulse Width
This time is long enough to initiate a double
read cycle by loading the High Speed
Registers (04H 05H) but is too short to
READ from 04H and 05H (See t_RLDV)
RD Low to Data Valid
(Only for Registers 02H 04H 05H)
8 MHz
4 MHz
2 MHz
7 5 ns
10 ns
30 ns
20 ns
10 ns
27 ns
10 ns
30 ns
8 ns
0 ns
40 ns
0 ns
16 MHz
10 MHz
8 MHz
55 ns
t_RLDV1
t_RHDZ
t_CLYV
RD Low Data to Data Valid (for Registers
except 02H 04H 05H)
for Read Cycle without a Previous Write⁽¹⁾
for Read Cycle with a Previous Write⁽¹⁾
Data Float after RD High
CS Low to READY Setup
Condition Load Capacitance on the READY
Output 50 pF
1 5 t_MCLK ^a 100 ns
3 5 t_MCLK ^a 100 ns
0 ns
45 ns
32 ns
40 ns
t_WLYZ
WR Low to READY Float for a Write Cycle
if No Previous Write is Pending⁽²⁾
145 ns
t_WHYZ
End of Last Write to READY Float for a Write
Cycle if a Previous Write Cycle is Active⁽²⁾
2 t_MCLK ^a 100 ns
t_RLYZ
RD Low to READY Float
(for registers except 02H 04H 05H)
for Read Cycle without a Previous Write⁽¹⁾
for Read Cycle with a Previous Write⁽¹⁾
2 t_MCLK ^a 100 ns
4 t_MCLK ^a 100 ns
Conditions
V_OL ^e 1 0V
V_OL ^e 0 45V
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