82527 Datasheet, PDF (4/22 Pages) Intel Corporation – SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL

82527
PIN DESCRIPTION
The 82527 pins are described in this section Table 1 presents the legend for interpreting the pin types
Table 1 Pin Type Legend
Symbol
Description
I
Input only pin
O
Output only pin
IO
Pin can be either input or output
PIN DESCRIPTIONS
Pin Name Pin Type
V_SS1
Ground
V_SS2
Ground
V_CC
Power
XTAL1
I
XTAL2
O
CLKOUT
O
RESET
I
CS
I
INT
O
(V_CC 2)
O
RX0
I
RX1
I
TX0
O
TX1
O
Pin Description
GROUND connection must be connected externally to a V_SS board plane
Provides digital ground
GROUND connection must be connected externally to a V_SS board plane
Provides ground for analog comparator
POWER connection must be connected externally to ^a5V DC Provides power
for entire device
Input for an external clock XTAL1 (along with XTAL2) are the crystal
connections to an internal oscillator
Push-pull output from the internal oscillator XTAL2 (along with XTAL1) are the
crystal connections to an internal oscillator If an external oscillator is used
XTAL2 must be floated or not be connected XTAL2 must not be used as a
clock output to drive other CPUs
Programmable clock output This output may be used to drive the oscillator of
the host microcontroller
Warm Reset (V_CC remains valid while RESET is asserted) RESET must be
driven to a valid low level for 1 ms minimum
Cold Reset (V_CC is driven to a valid level while RESET is asserted) RESET
must be driven low for 1 ms minimum measured from a valid V_CC level No
falling edge on the reset pin is required during a cold reset event
A low level on this pin enables CPU access to the 82527 device
The interrupt pin is an open-drain output to the host microcontroller V_CC 2 is
the power supply for the ISO low speed physical layer The function of this pin is
determined by the MUX bit in the CPU Interface Register (Address 02H) as
follows
MUX ^e 1 pin 24 (PLCC) ^e V_CC 2 pin 11 ^e INT
MUX ^e 0 pin 24 (PLCC) ^e INT
Inputs from the CAN bus line(s) to the input comparator A recessive level is
read when RX0 ^l RX1 A dominant level is read when RX1 ^l RX0 When the
CoBy bit (Bus Configuration register) is programmed as a ‘‘1’’ the input
comparator is bypassed and RX0 is the CAN bus line input
Serial data push-pull output to the CAN bus line During a recessive bit TX0 is
high and TX1 is low During a dominant bit TX0 is low and TX1 is high
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