82527 Datasheet, PDF (20/22 Pages) Intel Corporation – SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL

82527
15 Page 7 t_CLLL decreased from 20 ns to 10 ns
16 Page 3 RESET description addition
Warm reset (V_CC remains valid while RESET
is asserted) RESET must be driven to a valid
low level for 1 ms minimum
Cold reset (V_CC is driven to a valid level while
RESET is asserted RESET must be driven
low for 1 ms minimum measured from a valid
V_CC level No falling edge on the reset pin is
required during a cold reset event
17 Page 2 Figure 2 Pin 7 name changed to
(WR WRL ) (R W ) from WR (R W )
18 Page 4 pin description name changed to
(WR WRL ) (R W ) from WR (R W )
and WR in 8-bit Intel mode and WRL in
16-bit Intel mode replaces the description WR
used for Intel modes
19 Page 5 ABSOLUTE MAXIMUM RATINGS addi-
tion Laboratory testing shows the 82527 will
withstand up to 10 mA for injected current into
both RX0 and RX1 pins for a total of 20 days
without sustaining permanent damage This
high current condition may be the result of
shorted signal lines The 82527 will not function
properly if the RX0 RX1 input voltage exceeds
V_CC ^a 0 5V
20 Page 12 t_CHDV decreased from 25 ns to 15 ns
21 Page 14 t_ELDV decreased from 25 ns to 15 ns
22 Page 7 t_AVLL decreased from 20 ns to 7 5 ns
23 Page 7 t_WHQX decreased from 20 ns to 12 5 ns
This is the -003 revision of the 82527 data sheet
The following differences exist between the -002
version and the -003 revision
1 The data sheet has been revised to ADVANCE
from PRELIMINARY indicating the specifica-
tions have been verified through electrical tests
2 ABSOLUTE MAXIMUM RATINGS have been
added
3 V_IL no longer applies to the AD0 – AD7 pins in
CPU Interface mode 3
4 V_IL1 has been added to specify Input Low Volt-
age for AD0–AD7 pins in CPU Interface mode 3
as ^b0 5V minimum and ^a0 5V maximum
5 I_CC supply current has been reduced to 50 mA
from 100 mA
6 Note 2 was added stating during I_PD testing all
pins are driven to V_SS or V_CC including RX0
and RX1
7 t_AVLL has been decreased to 20 ns from 33 ns
8 t_RLDV1 has been decreased to 1 5 t_MCLK ^a 100
ns from 2 t_MCLK ^a 100 ns for a Read Cycle
without a previous Write (Modes 0 1)
t_RLDV1 has been decreased to 3 5 t_MCLK ^a 100
ns from 4 t_MCLK ^a 100 ns for a Read Cycle with
a previous Write (Modes 0 1)
9 t_CLYV has added the condition of V_OL ^e 1 0V
for a 32 ns delay t_CLYV is 40 ns for V_OL ^e 0 45
(Modes 0 1)
10 t_WHYZ has been decreased to 2 t_MCLK ^a
100 ns from 2 t_MCLK ^a 145 ns (Modes 0 1)
11 t_EHDV has been decreased to 1 5 t_MCLK ^a
100 ns from 2 t_MCLK ^a 100 ns for a Read Cycle
without a previous Write (Mode 2)
t_EHDV has been decreased to 3 5 t_MCLK ^a
100 ns from 4 t_MCLK ^a 100 ns for a Read Cycle
with a previous Write (Mode 2)
12 t_ELEL has been decreased to 2 t_MCLK from
2 t_MCLK ^a 145 ns (Mode 2)
13 t_CLDV has been decreased to 55 ns from 65 ns
(Mode 3)
14 t_CHKH is specified for V_IH ^e 2 4V decreased
from V_IH ^e 3 0V Note 3 has been added which
states an on-chip pullup will drive DSACK0 to
approximately 2 4V An external pullup is re-
quired to drive this signal to a higher voltage
(Mode 3)
15 t_CHAI has been increased to 10 ns from 5 ns
t_CHAI no longer includes CS High to R W
Invalid (Mode 3)
16 t_CHRI ^e 5 ns has been added to specify CS
High to R W Invalid (Mode 3)
17 t_EHDV has been decreased to 55 ns from 65 ns
for Reads of the High Speed Registers (Mode
3)
18 t_EHDV has been decreased to 1 5 t_MCLK ^a
100 ns from 2 t_MCLK ^a 100 ns for a Read Cycle
without a previous Write (Mode 3)
t_EHDV has been decreased to 3 5 t_MCLK ^a
100 ns from 4 t_MCLK ^a 100 ns for a Read Cycle
with a previous Write (Mode 3)
19 The t_AVAL specification name has been correct-
ed to t_AVAV (Mode 3)
20 t_CHAI has been increased to 10 ns from 5 ns
(Mode 3)
21 The input voltage in the A C Testing Input Dia-
gram have been revised to V_CC ^b 0 5V from
3 0V (high level) and revised to 0 1V from 0 8V
(low level)
20