82527 Datasheet, PDF (21/22 Pages) Intel Corporation – SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL

82527
The following differences exist between the -001
version and the -002 revision
1 The RAM block in Figure 1 82527 Block Dia-
gram was previously called DPRAM
2 The INT (V_CC 2) pin in Figure 2 44-Pin PLCC
Package and in other descriptions was previ-
ously called the INT (V_DD 2) pin
3 The Mode0 and Mode1 pin descriptions were
modified to include the following note These
pins are weakly held low during reset
4 The DSACK0 pin description was changed to
reflect an open-drain output
5 V_IL1 for RX0 in comparator bypass mode was
added
6 V_IH1 hysteresis on RESET was added
7 V_IH2 for RX0 in comparator bypass mode was
added
8 I_SLEEP current with V_CC 2 output enabled was
corrected from 700 mA minimum to 700 mA
maximum
9 I_SLEEP current with V_CC 2 output disabled was
corrected from 100 mA minimum to 100 mA
maximum
10 I_PD current was changed from 10 mA minimum
to 25 mA maximum
11 The following note was added to the electrical
characteristics Port pins are weakly held high
after reset until the port configuration registers
are written (9FH AFH)
12 The following D C Characteristics Specifica-
tions have been removed and replaced by the
Internal Delay 1 and Internal Delay 2 specifica-
tions These specifications reflect the produc-
tion test methodology which requires these two
delays to be tested together
a Delay Dominant to Recessive
b Delay Recessive to Dominant
c Input Delay with Comparator Bypassed
d Rise Time
e Fall Time
13 The following A C Characteristics for 8-Bit
16-Bit Multiplexed Intel Modes (Modes 0 1)
have been changed
a 1 t_MCLK has been increased to 8 MHz from
5 MHz
b t_LLAX has been decreased to 20 ns from
22 5 ns
c t_LLRL has been increased to 20 ns from
0 ns
d t_CLLL has been added
e t_WHLH has been increased to 8 ns from 0 ns
f t_WHCH has been added
g t_RLDV1 has been added
h t_WLYH has been changed to t_WLYZ to reflect
the READY pin is an open-drain output
i t_WHYH has been changed to t_WHYZ to re-
flect the READY pin is an open-drain output
j t_RLYH has been changed to t_RLYZ to reflect
the READY pin is an open-drain output
k t_WHDV has been increased to 2 t_MCLK ^a
250 ns from 2 t_MCLK ^a 100 ns
l The following note was added References
to WR also pertain to WRH
m The following definition was added for a
‘‘read cycle without a previous write’’ The
time between the rising edge of WR
WRH (for the previous write cycle) and the
falling edge of RD (for the current read cy-
cle) is greater than 2 t_MCLK
n The following definition was added for a
‘‘write cycle with a previous write’’ The time
between the rising edge of WR WRH
(for the previous write cycle) and the next
rising edge of WR WRH (for the current
write cycle) is less than 2 t_MCLK
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