82527 Datasheet, PDF (22/22 Pages) Intel Corporation – SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL

82527
14 The timing diagrams for 8-Bit 16-Bit Multiplexed
Intel Modes (Modes 0 1) have been changed to
show ALE rising before CS falls
15 The following A C Characteristics for 8-Bit Mul-
tiplexed Non-Intel Modes (Modes 2) have been
changed
a 1 t_MCLK has been increased to 8 MHz from
5 MHz
b t_SLAX has been decreased to 20 ns from
22 5 ns
c t_EVDV has been decreased to (2 4) t_MCLK ^a
100 ns from (2 4) t_MCLK ^a 145 ns
d t_ELDV minimum has been decreased to
t_MCLK from t_MCLK ^a 100 ns
e t_ELDV maximum has been increased to
2 t_MCLK ^a 500 ns from 2 t_MCLK ^a 100 ns
f t_EHEL for registers except 02H 04H 05H
has been renamed to t_ELEL and the specifi-
cation has been decreased to 2 t_MCLK ^a
145 ns from 4 t_MCLK ^a 145 ns
g t_SLEH has been increased to 20 ns from 0
ns
h t_CLSL has been added
i t_ELCH has been added
j The following definition was added for a
‘‘read cycle without a previous write’’ The
time between the falling edge of E (for the
previous write cycle) and the rising edge of
E (for the current read cycle) is greater than
2 t_MCLK
k The following definition was added for a
‘‘write cycle with a previous write’’ The time
between the falling edge of E (for the previ-
ous write cycle) and the next falling edge of
E (for the current write cycle) is less than
2 t_MCLK
16 The following A C Characteristics for 8-Bit Non-
Multiplexed Asynchronous Mode (Mode 3) have
been changed
a 1 t_MCLK has been increased to 8 MHz from
5 MHz
b t_CLDV has been decreased for low speed
registers to (2 4) t_MCLK ^a 100 ns from
(2 4) t_MCLK ^a 145 ns
c t_CHKH comment ‘‘with 3 3 KX Pullup and
100 pF Load’’ has been removed since
t_CHKH is tested with a current source
d t_CLKL for a Write Access with a Previous
Write has been renamed to t_CHKL
e The note ‘‘E and AS must be tied high in this
mode’’ has been added
f The following definition was added for a
‘‘read cycle without a previous write’’ The
time between the rising edge of CS (for
the previous write cycle) and the falling edge
of CS (for the current read cycle) is great-
er than 2 t_MCLK
g The following definition was added for a
‘‘write cycle with a previous write’’ The time
between the rising edge of CS (for the pre-
vious write cycle) and the next rising edge of
CS (for the current write cycle) is less than
2 t_MCLK
17 The following A C Characteristics for 8-Bit Non-
Multiplexed Synchronous Mode (Mode 3) have
been changed
a 1 t_MCLK has been increased to 8 MHz from
5 MHz
b t_ELDZ minimum has been removed
c t_AVCL has been added
d t_CHAI has been added
e The following definition was added for a
‘‘read cycle without a previous write’’ The
time between the falling edge of E (for the
previous write cycle) and the rising edge of
E (for the current read cycle) is greater than
2 t_MCLK
f The following definition was added for a
‘‘write cycle with a previous write’’ The time
between the falling edge of E (for the previ-
ous write cycle) and the next falling edge of
E (for the current write cycle) is less than
2 t_MCLK
18 The following A C Characteristics for Serial In-
terface Mode have been changed
a t_SKHI has been decreased to 84 ns from
119 ns
b t_SKLO has been decreased to 84 ns from
119 ns
c t_PDO has been decreased to 59 ns from
84 ns
d t_SETUP has been decreased to 35 ns from
59 ns
e t_HOLD has been decreased to 84 ns from
109 ns
19 The note in the A C Testing Input diagram refer-
enced V_OH was previously named V_IH
22