82527 Datasheet, PDF (19/22 Pages) Intel Corporation – SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL

82527
3 Removed XTAL1 and XTAL2 from the excep-
tions for V_IL spec XTAL1 V_IL is now specified at
min ^{e b}0 5V max ^e 0 8V XTAL2 is an output
4 Removed XTAL1 and XTAL2 from the excep-
tions for V_IH spec XTAL1 V_IH is now specified at
min ^e 3 0V max ^e V_CC ^a 0 5V XTAL2 is an
output
5 Source and Sink current for TX0 and TX1 were
corrected from minimum values to maximum val-
ues
6 Mode 2 The t_AVSL specification was decreased
to 7 5 ns from 33 ns
7 Mode 2 The t_SLAX specification was decreased
to 10 ns from 20 ns
8 Mode 3 Asynchronous The t_DVCH specification
was decreased to 20 ns from 32 ns
9 All modes Two specifications were added for
CLKOUT These specifications are t_COPD
(CLKOUT Period) ^e (CD_V ^a 1) t_OSC and t_CHCL
(CLKOUT High Period) ^e min (CD_v ^a 1)
t_OSC ^b 10 ns and max (CD_V ^a 1)
t_OSC ^a
15 ns NOTE CD_V represented the value loaded
in the lower nibble of the CLKOUT Register
(1FH)
10 Serial Interface Mode The maximum SCLK (SPI
Clock) rate was increased to 8 MHz from 4 2
MHz The minimum t_CYC (1 SCLK) was set at
125 ns from 238 ns to reflect the increased max-
imum SPI clock rate
11 MODE0 1 the t_WHQX Specifications was de-
creased to 10 ns from 12 5 ns
This is the -004 revision of the 82527 data sheet
The following differences exist between the -003
version and the -004 revision
1 Remove notice on page 1 concerning Advance
Information Data Sheet
2 Page 4 AS pin description add ‘‘pin tied high in
Asycnhronous mode 3’’
3 Page 4 E pin description add ‘‘pin tied high in
mode 3’’
4 Page 5 add V_IH ^e 0 7 V_CC and V_IL ^e 0 3 V_CC
for LSIO port pins (pins not used to interface to
host-CPU)
5 Page 6 change Differential Input Threshold
from MAX spec to MIN spec
6 Page 6 add Input Hysteresis spec for RX0 RX1
e _{0V maximum}
7 Page 7 t_LLAX decreased from 20 ns to 10 ns (to
interface to 20 MHz C196)
8 Page 7 t_QVWH decreased from 30 ns to 27 ns
(to interface to 20 MHz C196)
9 Page 7 t_WLWH decreased from 40 ns to 30 ns
(to interface to 20 MHz C196)
10 Page 7 t_RLDV increased from 45 ns to 55 ns
11 Page 12 t_CHKH specification added for V_IH ^e
2 8V ^e 150 ns
12 Page 12 t_CHAI decreased from 10 ns to 7 ns
13 Page 13 timing diagram for t_AVCL revised to
show common CL low level
14 Page 14 t_CHAI decreased from 10 ns to 7 ns
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