82527 Datasheet, PDF (11/22 Pages) Intel Corporation – SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL

82527
A C Characteristics for 8-Bit Multiplexed Non-Intel Mode (Mode 2)
Conditions V_CC ^e 5V g10% V_SS ^e 0V T_A ^{e b}40 C to ^a125 C C_L ^e 100 pF
Symbol
Parameter
Min
Max
1 t_XTAL Oscillator Frequency
1 t_SCLK System Clock Frequency
1 t_MCLK Memory Clock Frequency
t_AVSL Address Valid to AS Low
t_SLAX Address Hold after AS Low
t_ELDZ Data Float after E Low
t_EHDV E High to Data Valid for Registers 02H
04H 05H
8 MHz
4 MHz
2 MHz
7 5 ns
10 ns
0 ns
0 ns
16 MHz
10 MHz
8 MHz
45 ns
45 ns
for Read Cycle without a Previous Write⁽¹⁾
for Read Cycle with a Previous Write
(for Registers except for 02H 04H 05H)
1 5 t_MCLK ^a 100 ns
3 5 t_MCLK ^a 100 ns
t_QVEL
t_ELQX
t_ELDV
t_EHEL
t_ELEL
Data Setup to E Low
Input Data Hold after E Low
E Low to Output Data Valid on Port 1 2
E High Time
End of Previous Write (Last E Low) to E
Low for a Write Cycle
30 ns
20 ns
t_MCLK
45 ns
2 t_MCLK
2 t_MCLK ^a 500 ns
t_SHSL
t_RSEH
t_SLEH
t_CLSL
t_ELCH
t_COPD
t_CHCL
AS High Time
Setup Time of R W to E High
AS Low to E High
CS Low to AS Low
E Low to CS High
CLKOUT Period
CLKOUT High Period
30 ns
30 ns
20 ns
20 ns
0 ns
(CD_V ^a 1)
(CD_V ^a 1) t_OSC(3)
t_OSC ^b 10 (CD_V ^a 1)
t_OSC ^a 15
NOTES
1 Definition of ‘‘Read Cycle without a Previous Write’’ The time between the falling edge of E (for the previous write cycle)
and the rising edge of E (for the current read cycle) is greater than 2 t_MCLK
2 Definition of ‘‘Write Cycle with a Previous Write’’ The time between the falling edge of E (for the previous write cycle) and
the falling edge of E (for the current write cycle) is less than 2 t_MCLK
3 Definition of CD_V is the value loaded in the CLKOUT register representing the CLKOUT divisor
11