82527 Datasheet, PDF (13/22 Pages) Intel Corporation – SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL

82527
A C Characteristics for 8-Bit Non-Multiplexed Asynchronous (Mode 3)
Conditions V_CC ^e 5V g10% V_SS ^e 0V T_A ^{e b}40 C to ^a125 C C_L ^e 100 pF
Symbol
Parameter
Min
Max
1 t_XTAL Oscillator Frequency
1 t_SCLK System Clock Frequency
1 t_MCLK Memory Clock Frequency
t_AVCL
Address or R W Valid to CS Low
Setup
8 MHz
4 MHz
2 MHz
3 ns
16 MHz
10 MHz
8 MHz
t_CLDV CS Low to Data Valid
0 ns
for High Speed Registers (02H 04H 05H)
55 ns
For Low Speed Registers
0 ns
1 5 t_MCLK ^a 100 ns
(Read Cycle without Previous Write)⁽¹⁾
For Low Speed Registers
(Read Cycle with Previous Write)⁽¹⁾
0 ns
3 5 t_MCLK ^a 100 ns
t_KLDV
DSACK0 Low to Output Data Valid
for High Speed Read Register
23 ns
For Low Speed Read Register
k_{0 ns}
t_CHDV
t_CHDH
t_CHDZ
t_CHKH1
t_CHKH2
t_CHKZ
t_CHCL
t_CHAI
t_CHRI
t_CLCH
t_DVCH
t_CLKL
82527 Input Data Hold after CS High
82527 Output Data Hold after CS High
CS High to Output Data Float
CS High to DSACK0 ^e 2 4V⁽³⁾
CS High to DSACK0 ^e 2 8V
CS High to DSACK0 Float
CS Width between Successive Cycles
CS High to Address Invalid
CS High to R W Invalid
CS Width Low
CPU Write Data Valid to CS High
CS Low to DSACK0 Low
for High Speed Registers and Low Speed
Registers Write Access without Previous
Write⁽²⁾
15 ns
0 ns
0 ns
0 ns
25 ns
7 ns
5 ns
65 ns
20 ns
0 ns
35 ns
55 ns
150 ns
100 ns
67 ns
t_CHKL End of Previous Write (CS High) to
0 ns
DSACK0 Low for a Write Cycle with a
Previous Write⁽²⁾
2 t_MCLK ^a 145 ns
t_COPD
t_CHCL
CLKOUT Period
CLKOUT High Period
(CD_V ^a 1)
(CD_V ^a 1) t_OSC(4)
t_OSC ^b 10 (CD_V ^a 1)
t_OSC ^a 15
NOTES
E and AS must be tied high in this mode
1 Definition of ‘‘Read Cycle without a Previous Write’’ The time between the rising edge of CS (for the previous write
cycle) and the falling edge of CS (for the current read cycle) is greater than 2 t_MCLK
2 Definition of ‘‘Write Cycle without a Previous Write’’ The time between the rising edge of CS (for the previous write
cycle) and the rising edge of CS (for the current write cycle) is greater than 2 t_MCLK
3 An on-chip pullup will drive DSACK0 to approximately 2 4V An external pullup is required to drive this signal to a higher
voltage
4 Definition of CD_V is the value loaded in the CLKOUT register representing the CLKOUT divisor
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