82527 Datasheet, PDF (15/22 Pages) Intel Corporation – SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL

82527
A C Characteristics for 8-Bit Non-Multiplexed Synchronous Mode (Mode 3)
Conditions V_CC ^e 5V g10% V_SS ^e 0V T_A ^{e b}40 C to ^a125 C C_L ^e 100 pF
Symbol
Parameter
Min
Max
1 t_XTAL
1 t_SCLK
1 t_MCLK
t_EHDV
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
E High to Data Valid out of High Speed
Register (02H 04H 05H)
8 MHz
4 MHz
2 MHz
16 MHz
10 MHz
8 MHz
55 ns
Read Cycle without Previous Write for
Low Speed Registers⁽¹⁾
1 5 t_MCLK ^a 100 ns
Read Cycle with Previous Write for
Low Speed Registers⁽¹⁾
3 5 t_MCLK ^a 100 ns
t_ELDH Data Hold after E Low for a Read
5 ns
Cycle
t_ELDZ
t_ELDV
t_AVEH
t_ELAV
t_CVEH
t_ELCV
t_DVEL
t_EHEL
t_AVAV
Data Float after E Low
Data Hold after E Low for a Write Cycle
Address and R W to E Setup
Address and R W Valid after E Falls
CS Valid to E High
CS Valid after E Low
Data Setup to E Low
E Active Width
Start of a Write Cycle after a Previous
Write Access
15 ns
25 ns
15 ns
0 ns
0 ns
55 ns
100 ns
2 t_MCLK
35 ns
t_AVCL
t_CHAI
t_COPD
t_CHCL
Address or R W to CS Low Setup
CS High to Address Invalid
CLKOUT Period
CLKOUT High Period
3 ns
7 ns
(CD_V ^a 1)
(CD_V ^a 1) t_OSC(2)
t_OSC ^b 10 (CD_V ^a 1)
t_OSC ^a 15
NOTES
1 Definition of ‘‘Read Cycle without a Previous Write’’ The time between the falling edge of E (for the previous write cycle)
and the rising edge of E (for the current read cycle) is greater than 2 t_MCLK
2 Definition of CD_V is the value loaded in the CLKOUT register representing the CLKOUT divisor
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