80186 Datasheet, PDF (8/33 Pages) Intel Corporation – HIGH-INTEGRATION 16-BIT MICROPROCESSORS

80186 80188
Table 1 Pin Descriptions (Continued)
Symbol
Pin
No
Type
Name and Function
HOLD
HLDA
50
I
HOLD indicates that another bus master is requesting the local bus The
51
O HOLD input is active HIGH HOLD may be asynchronous with respect to the
processor clock The processor will issue a HLDA (HIGH) in response to a
HOLD request at the end of T₄ or T_i Simultaneous with the issuance of
HLDA the processor will float the local bus and control lines After HOLD is
detected as being LOW the processor will lower HLDA When the processor
needs to run another bus cycle it will again drive the local bus and control
lines
UCS
34
O Upper Memory Chip Select is an active LOW output whenever a memory
reference is made to the defined upper portion (1K – 256K block) of memory
This line is not floated during bus HOLD The address range activating UCS is
software programmable
LCS
33
O Lower Memory Chip Select is active LOW whenever a memory reference is
made to the defined lower portion (1K – 256K) of memory This line is not
floated during bus HOLD The address range activating LCS is software
programmable
MCS0
MCS1
MCS2
MCS3
38
O Mid-Range Memory Chip Select signals are active LOW when a memory
37
O reference is made to the defined mid-range portion of memory (8K – 512K)
36
O ^{These lines are not floated during bus HOLD The address ranges activating}
35
O
MCS0 –3 are software programmable
PCS0
PCS1
PCS2
PCS3
PCS4
25
O Peripheral Chip Select signals 0 – 4 are active LOW when a reference is made
27
O to the defined peripheral area (64 Kbyte I O space) These lines are not
28
O ^{floated during bus HOLD The address ranges activating PCS0 – 4 are}
29
O
software programmable
30
O
PCS5 A1 31
O Peripheral Chip Select 5 or Latched A1 may be programmed to provide a
sixth peripheral chip select or to provide an internally latched A1 signal The
address range activating PCS5 is software-programmable PCS5 A1 does
not float during bus HOLD When programmed to provide latched A1 this pin
will retain the previously latched value during HOLD
PCS6 A2 32
O Peripheral Chip Select 6 or Latched A2 may be programmed to provide a
seventh peripheral chip select or to provide an internally latched A2 signal
The address range activating PCS6 is software programmable PCS6 A2
does not float during bus HOLD When programmed to provide latched A2
this pin will retain the previously latched value during HOLD
DT R
40
O Data Transmit Receive controls the direction of data flow through an
external data bus transceiver When LOW data is transferred to the
processsor When HIGH the processor places write data on the data bus
DEN
39
O Data Enable is provided as a data bus transceiver output enable DEN is
active LOW during each memory and I O access DEN is HIGH whenever
DT R changes state During RESET DEN is driven HIGH for one clock then
floated DEN also floats during HOLD
NOTE
Pin names in parentheses apply to the 80188
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