80186 Datasheet, PDF (12/33 Pages) Intel Corporation – HIGH-INTEGRATION 16-BIT MICROPROCESSORS

80186 80188
TIMERS AND RESET
Upon RESET the Timers will perform the following
actions
 All EN (Enable) bits are reset preventing timer
counting
 For Timers 0 and 1 the RIU bits are reset to zero
and the ALT bits are set to one This results in the
Timer Out pins going high
Interrupt Controller
The processor can receive interrupts from a number
of sources both internal and external The internal
interrupt controller serves to merge these requests
on a priority basis for individual service by the CPU
Internal interrupt sources (Timers and DMA chan-
nels) can be disabled by their own control registers
or by mask bits within the interrupt controller The
interrupt controller has its own control register that
sets the mode of operation for the controller
INTERRUPT CONTROLLER AND RESET
Upon RESET the interrupt controller will perform
the following actions
 All SFNM bits reset to 0 implying Fully Nested
Mode
 All PR bits in the various control registers set to 1
This places all sources at lowest priority (level
111)
 All LTM bits reset to 0 resulting in edge-sense
mode
 All Interrupt Service bits reset to 0
 All Interrupt Request bits reset to 0
 All MSK (Interrupt Mask) bits set to 1 (mask)
 All C (Cascade) bits reset to 0 (non-Cascade)
 All PRM (Priority Mask) bits set to 1 implying no
levels masked
 Initialized to Master Mode
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