80186 Datasheet, PDF (6/33 Pages) Intel Corporation – HIGH-INTEGRATION 16-BIT MICROPROCESSORS

80186 80188
Table 1 Pin Descriptions (Continued)
Symbol
Pin
No
Type
Name and Function
A19 S6
A18 S5
A17 S4
A16 S3
65 O Address Bus Outputs (16–19) and Bus Cycle Status (3–6) indicate the four most
66 O significant address bits during T₁ These signals are active HIGH During T₂ T₃ T_W
67 O and T4 the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a
68 O ^{DMA-initiated bus cycle During the same T-states S3 S4 and S5 are always LOW}
The status pins float during bus HOLD or RESET
AD15 (A15) 1
AD14 (A14) 3
AD13 (A13) 5
AD12 (A12) 7
AD11 (A11) 10
AD10 (A10) 12
AD9 (A9) 14
AD8 (A8) 16
AD7
2
AD6
4
AD5
6
AD4
8
AD3
11
AD2
13
AD1
15
AD0
17
I O Address Data Bus signals constitute the time multiplexed memory or I O address (T₁)
I O and data (T₂ T₃ T_W and T₄) bus The bus is active HIGH A₀ is analogous to BHE for
I O the lower byte of the data bus pins D7 through D0 It is LOW during T1 when a byte is
I O ^{to be transferred onto the lower portion of the bus in memory or I O operations BHE}
I O ^{does not exist on the 80188 as the data bus is only 8 bits wide}
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BHE S7
(S7)
64 O During T₁ the Bus High Enable signal should be used to determine if data is to be
enabled onto the most significant half of the data bus pins D₁₅–D₈ BHE is LOW
during T₁ for read write and interrupt acknowledge cycles when a byte is to be
transferred on the higher half of the bus The S₇ status information is available during
T₂ T₃ and T₄ S₇ is logically equivalent to BHE BHE S7 floats during HOLD On the
80188 S7 is high during normal operation
BHE and A0 Encodings (80186 Only)
BHE A0
Value Value
Function
0
0 Word Transfer
0
1 Byte Transfer on upper half of data bus (D15–D8)
1
0 Byte Transfer on lower half of data bus (D₇–D₀)
1
1 Reserved
ALE QS0 61 O Address Latch Enable Queue Status 0 is provided by the processor to latch the
address ALE is active HIGH Addresses are guaranteed to be valid on the trailing
edge of ALE The ALE rising edge is generated off the rising edge of the CLKOUT
immediately preceding T₁ of the associated bus cycle effectively one-half clock cycle
earlier than in the 8086 The trailing edge is generated off the CLKOUT rising edge in
T₁ as in the 8086 Note that ALE is never floated
WR QS1
63 O Write Strobe Queue Status 1 indicates that the data on the bus is to be written into a
memory or an I O device WR is active for T₂ T₃ and T_W of any write cycle It is active
LOW and floats during HOLD When the processor is in queue status mode the ALE
QS0 and WR QS1 pins provide information about processor instruction queue
interaction
QS1 QS0
Queue Operation
0
0 No queue operation
0
1 First opcode byte fetched from the queue
1
1 Subsequent byte fetched from the queue
1
0 Empty the queue
NOTE
Pin names in parentheses apply to the 80188
6
6