80186 Datasheet, PDF (16/33 Pages) Intel Corporation – HIGH-INTEGRATION 16-BIT MICROPROCESSORS

80186 80188
A C CHARACTERISTICS (T_A ^e 0 C to ^a70 C V_CC ^e 5V g10%)
Timing Requirements All Timings Measured At 1 5V Unless Otherwise Noted
Symbol
Parameter
8 MHz
Min
Max
10 MHz
Units
Min
Max
Test
Conditions
T_DVCL
Data in Setup (A D)
20
T_CLDX
Data in Hold (A D)
10
T_ARYHCH Asynchronous Ready
20
(ARDY) Active Setup
Time⁽¹⁾
15
ns
8
ns
15
ns
T_ARYLCL ARDY Inactive Setup Time
35
T_CLARX ARDY Hold Time
15
T_ARYCHL Asynchronous Ready
15
Inactive Hold Time
25
ns
15
ns
15
ns
T_SRYCL Synchronous Ready (SRDY)
20
Transition Setup Time⁽²⁾
20
ns
T_CLSRY SRDY Transition Hold
15
Time⁽²⁾
15
ns
T_HVCL
HOLD Setup⁽¹⁾
25
T_INVCH INTR NMI TEST TIM IN
25
Setup⁽¹⁾
20
ns
25
ns
T_INVCL
DRQ0 DRQ1 Setup⁽¹⁾
25
Master Interface Timing Responses
20
ns
T_CLAV
T_CLAX
T_CLAZ
Address Valid Delay
Address Hold
Address Float Delay
5
55
5
44 ns C_L e 20 pF–200 pF
all Outputs
10
10
ns _{(Except TCLTMV)}
T_CLAX
35
T_CLAX
30 ns 8 MHz and 10 MHz
T_CHCZ
Command Lines Float Delay
45
40 ns
T_CHCV
Command Lines Valid Delay
55
45 ns
(after Float)
T_LHLL
T_CHLH
T_CHLL
T_LLAX
ALE Width
ALE Active Delay
ALE Inactive Delay
Address Hold from ALE
Inactive
T_CLCLb35
T_CLCLb30
ns
35
30 ns
35
30 ns
T_CHCLb25
T_CHCLb20
ns
T_CLDV
Data Valid Delay
T_CLDOX Data Hold Time
T_WHDX Data Hold after WR
T_CVCTV Control Active Delay 1
T_CHCTV Control Active Delay 2
T_CVCTX Control Inactive Delay
T_CVDEX DEN Inactive Delay
(Non-Write Cycle)
1 To guarantee recognition at next clock
2 To guarantee proper operation
10
44
10
40 ns
10
10
ns
T_CLCLb40
T_CLCLb34
ns
5
50
5
40 ns
10
55
10
44 ns
5
55
5
44 ns
10
70
10
56 ns
16
16