80186 Datasheet, PDF (17/33 Pages) Intel Corporation – HIGH-INTEGRATION 16-BIT MICROPROCESSORS

80186 80188
A C CHARACTERISTICS (T_A ^e 0 C to ^a70 C V_CC ^e 5V g10%) (Continued)
Master Interface Timing Responses (Continued)
Symbol
Parameter
8 MHz
Min
Max
10 MHz
Units
Min
Max
Test
Conditions
T_AZRL
T_CLRL
T_CLRH
T_RHAV
Address Float to RD Active
RD Active Delay
RD Inactive Delay
RD Inactive to Address
Active
0
0
ns
10
70
10
56 ns
10
55
10
44 ns
T_CLCLb40
T_CLCLb40
ns
T_CLHAV
T_RLRH
T_WLWH
T_AVLL
T_CHSV
T_CLSH
T_CLTMV
HLDA Valid Delay
RD Width
WR Width
Address Valid to ALE Low
Status Active Delay
Status Inactive Delay
Timer Output Delay
5
50
5
40
2T_CLCLb50
2T_CLCLb40
T_CLCHb25
2T_CLCLb46
2T_CLCLb34
T_CLCHb19
10
55
10
45
10
65
10
50
60
48
ns
ns
ns
ns
ns
ns
ns 100 pF max
8 10 MHz
T_CLRO Reset Delay
T_CHQSV Queue Status Delay
T_CHDX Status Hold Time
T_AVCH Address Valid to Clock High
T_CLLV
LOCK Valid Invalid Delay
Chip-Select Timing Responses
60
48 ns
35
28 ns
10
10
ns
10
10
ns
5
65
5
60 ns
T_CLCSV
T_CXCSX
Chip-Select Active Delay
Chip-Select Hold from
Command Inactive
66
45 ns
35
35
ns
T_CHCSX Chip-Select Inactive Delay
CLKIN Requirements
5
35
5
32 ns
T_CKIN
CLKIN Period
T_CKHL CLKIN Fall Time
T_CKLH CLKIN Rise Time
T_CLCK CLKIN Low Time
T_CHCK CLKIN High Time
CLKOUT Timing (200 pF load)
62 5
250
50
250 ns
10
10 ns 3 5 to 1 0V
10
10 ns 1 0 to 3 5V
25
20
ns 1 5V
25
20
ns 1 5V
T_CICO
T_CLCL
T_CLCH
T_CHCL
T_CH1CH2
T_CL2CL1
CLKIN to CLKOUT Skew
CLKOUT Period
CLKOUT Low Time
CLKOUT High Time
CLKOUT Rise Time
CLKOUT Fall Time
50
125
500
T_CLCLb7 5
T_CLCLb7 5
15
15
25 ns
100
500 ns
T_CLCLb6 0
T_CLCLb6 0
12
ns 1 5V
ns 1 5V
ns 1 0 to 3 5V
12 ns 3 5 to 1 0V
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