80186 Datasheet, PDF (7/33 Pages) Intel Corporation – HIGH-INTEGRATION 16-BIT MICROPROCESSORS

80186 80188
Table 1 Pin Descriptions (Continued)
Symbol
Pin
No
Type
Name and Function
RD QSMD 62
I O Read Strobe is an active LOW signal which indicates that the processor is
performing a memory or I O read cycle It is guaranteed not to go LOW
before the A D bus is floated An internal pull-up ensures that RD is HIGH
during RESET Following RESET the pin is sampled to determine whether
the processor is to provide ALE RD and WR or queue status information
To enable Queue Status Mode RD must be connected to GND RD will
float during bus HOLD
ARDY
55
I
Asynchronous Ready informs the processor that the addressed memory
space or I O device will complete a data transfer The ARDY pin accepts a
rising edge that is asynchronous to CLKOUT and is active HIGH The
falling edge of ARDY must be synchronized to the processor clock
Connecting ARDY HIGH will always assert the ready condition to the CPU
If this line is unused it should be tied LOW to yield control to the SRDY pin
SRDY
49
I
Synchronous Ready informs the processor that the addressed memory
space or I O device will complete a data transfer The SRDY pin accepts an
active-HIGH input synchronized to CLKOUT The use of SRDY allows a
relaxed system timing over ARDY This is accomplished by elimination of
the one-half clock cycle required to internally synchronize the ARDY input
signal Connecting SRDY high will always assert the ready condition to the
CPU If this line is unused it should be tied LOW to yield control to the
ARDY pin
LOCK
48
O LOCK output indicates that other system bus masters are not to gain
control of the system bus while LOCK is active LOW The LOCK signal is
requested by the LOCK prefix instruction and is activated at the beginning
of the first data cycle associated with the instruction following the LOCK
prefix It remains active until the completion of that instruction No
instruction prefetching will occur while LOCK is asserted When executing
more than one LOCK instruction always make sure there are 6 bytes of
code between the end of the first LOCK instruction and the start of the
second LOCK instruction LOCK is driven HIGH for one clock during RESET
and then floated
S0
52
O Bus cycle status S0 –S2 are encoded to provide bus-transaction
S1
53
O information
S2
54
O
Bus Cycle Status Information
S2 S1 S0
Bus Cycle Initiated
0 0 0 Interrupt Acknowledge
0 0 1 Read I O
0 1 0 Write I O
0 1 1 Halt
1 0 0 Instruction Fetch
1 0 1 Read Data from Memory
1 1 0 Write Data to Memory
1 1 1 Passive (no bus cycle)
The status pins float during HOLD
S2 may be used as a logical M IO indicator and S1 as a DT R indicator
NOTE
Pin names in parentheses apply to the 80188
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