80186 Datasheet, PDF (10/33 Pages) Intel Corporation – HIGH-INTEGRATION 16-BIT MICROPROCESSORS

80186 80188
Memory Peripheral Control
The processor provides ALE RD and WR bus con-
trol signals The RD and WR signals are used to
strobe data from memory or I O to the processor or
to strobe data from the processor to memory or I O
The ALE line provides a strobe to latch the address
when it is valid The local bus controller does not
provide a memory I O signal If this is required use
the S2 signal (which will require external latching)
make the memory and I O spaces nonoverlapping
or use only the integrated chip-select circuitry
Local Bus Arbitration
The processor uses a HOLD HLDA system of local
bus exchange This provides an asynchronous bus
exchange mechanism This means multiple masters
utilizing the same bus can operate at separate clock
frequencies The processor provides a single
HOLD HLDA pair through which all other bus mas-
ters may gain control of the local bus External cir-
cuitry must arbitrate which external device will gain
control of the bus when there is more than one alter-
nate local bus master When the processor relin-
quishes control of the local bus it floats DEN RD
WR S0–S2 LOCK AD0–AD15 (AD0–AD7)
A16–A19 (A8–A19) BHE (S7) and DT R to allow
another master to drive these lines directly
Local Bus Controller and Reset
During RESET the local bus controller will perform
the following action
 Drive DEN RD and WR HIGH for one clock cy-
cle then float
NOTE
RD is also provided with an internal pull-up de-
vice to prevent the processor from inadvertently
entering Queue Status Mode during RESET
 Drive S0–S2 to the inactive state (all HIGH) and
then float
 Drive LOCK HIGH and then float
 Float AD0–15 (AD0–AD7) A16–19 (A8–A19)
BHE (S7) DT R
 Drive ALE LOW (ALE is never floated)
 Drive HLDA LOW
either memory or I O space Internal logic will recog-
nize control block addresses and respond to bus cy-
cles During bus cycles to internal registers the bus
controller will signal the operation externally (i e the
RD WR status address data etc lines will be driv-
en as in a normal bus cycle) but D_15–0 (D_7–0)
SRDY and ARDY will be ignored The base address
of the control block must be on an even 256-byte
boundary (i e the lower 8 bits of the base address
are all zeros)
The control block base address is programmed by a
16-bit relocation register contained within the control
block at offset FEH from the base address of the
control block It provides the upper 12 bits of the
base address of the control block
In addition to providing relocation information for the
control block the relocation register contains bits
which place the interrupt controller into Slave Mode
and cause the CPU to interrupt upon encountering
ESC instructions
Chip-Select Ready Generation Logic
The processor contains logic which provides
programmable chip-select generation for both mem-
ories and peripherals In addition it can be pro-
grammed to provide READY (or WAIT state) genera-
tion It can also provide latched address bits A1 and
A2 The chip-select lines are active for all memory
and I O cycles in their programmed areas whether
they be generated by the CPU or by the integrated
DMA unit
MEMORY CHIP SELECTS
The processor provides 6 memory chip select out-
puts for 3 address areas upper memory lower
memory and midrange memory One each is provid-
ed for upper memory and lower memory while four
are provided for midrange memory
UPPER MEMORY CS
The processor provides a chip select called UCS
for the top of memory The top of memory is usually
used as the system memory because after reset the
processor begins executing at memory location
FFFF0H
PERIPHERAL ARCHITECTURE
All of the integrated peripherals are controlled by
16-bit registers contained within an internal 256-byte
control block The control block may be mapped into
LOWER MEMORY CS
The processor provides a chip select for low memo-
ry called LCS The bottom of memory contains the
interrupt vector table starting at location 00000H
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