80186 Datasheet, PDF (11/33 Pages) Intel Corporation – HIGH-INTEGRATION 16-BIT MICROPROCESSORS

80186 80188
The lower limit of memory defined by this chip select
is always 0H while the upper limit is programmable
By programming the upper limit the size of the
memory block is defined
MID-RANGE MEMORY CS
The processor provides four MCS lines which are
active within a user-locatable memory block This
block can be located within the 1-Mbyte memory ad-
dress space exclusive of the areas defined by UCS
and LCS Both the base address and size of this
memory block are programmable
PERIPHERAL CHIP SELECTS
The processor can generate chip selects for up to
seven peripheral devices These chip selects are ac-
tive for seven contiguous blocks of 128 bytes above
a programmable base address The base address
may be located in either memory or I O space Sev-
en CS lines called PCS0 –6 are generated by the
processor PCS5 and PCS6 can also be pro-
grammed to provide latched address bits A1 and A2
If so programmed they cannot be used as peripher-
al selects These outputs can be connected directly
to the A0 and A1 pins used for selecting internal
registers of 8-bit peripheral chips
READY GENERATION LOGIC
The processor can generate a READY signal inter-
nally for each of the memory or peripheral CS lines
The number of WAIT states to be inserted for each
peripheral or memory is programmable to provide
0–3 wait states for all accesses to the area for
which the chip select is active In addition the proc-
essor may be programmed to either ignore external
READY for each chip-select range individually or to
factor external READY with the integrated ready
generator
CHIP SELECT READY LOGIC AND RESET
Upon RESET the Chip-Select Ready Logic will per-
form the following actions
 All chip-select outputs will be driven HIGH
 Upon leaving RESET the UCS line will be pro-
grammed to provide chip selects to a 1K block
with the accompanying READY control bits set at
011 to insert 3 wait states in conjunction with ex-
ternal READY (i e UMCS resets to FFFBH)
 No other chip select or READY control registers
have any predefined values after RESET They
will not become active until the CPU accesses
their control registers Both the PACS and MPCS
registers must be accessed before the PCS lines
will become active
DMA Channels
The DMA controller provides two independent DMA
channels Data transfers can occur between memo-
ry and I O spaces (e g Memory to I O) or within the
same space (e g Memory to Memory or I O to I O)
Data can be transferred either in bytes or in words
(80186 only) to or from even or odd addresses
Each DMA channel maintains both a 20-bit source
and destination pointer which can be optionally in-
cremented or decremented after each data transfer
(by one or two depending on byte or word transfers)
Each data transfer consumes 2 bus cycles (a mini-
mum of 8 clocks) one cycle to fetch data and the
other to store data This provides a maximum data
transfer rate of 1 25 Mword sec or 2 5 Mbytes sec
at 10 MHz (half of this rate for the 80188)
DMA CHANNELS AND RESET
Upon RESET the DMA channels will perform the
following actions
 The Start Stop bit for each channel will be reset
to STOP
 Any transfer in progress is aborted
Timers
The processor provides three internal 16-bit pro-
grammable timers Two of these are highly flexible
and are connected to four external pins (2 per timer)
They can be used to count external events time ex-
ternal events generate nonrepetitive waveforms
etc The third timer is not connected to any external
pins and is useful for real-time coding and time de-
lay applications In addition the third timer can be
used as a prescaler to the other two or as a DMA
request source
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